Intel® Agilex™ Clocking and PLL User Guide

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ID 683761
Date 11/09/2022
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Document Table of Contents
Document Table of Contents x
1. Intel® Agilex™ Clocking and PLL Overview 2. Intel® Agilex™ Clocking and PLL Architecture and Features 3. Intel® Agilex™ Clocking and PLL Design Considerations 4. Clock Control Intel® FPGA IP Core 5. IOPLL Intel® FPGA IP Core 6. IOPLL Reconfig Intel® FPGA IP Core 7. Intel® Agilex™ Clocking and PLL User Guide Archives 8. Document Revision History for the Intel® Agilex™ Clocking and PLL User Guide
1. Intel® Agilex™ Clocking and PLL Overview x
1.1. Clock Networks Overview 1.2. PLLs Overview
2. Intel® Agilex™ Clocking and PLL Architecture and Features x
2.1. Clock Networks Architecture and Features 2.2. PLLs Architecture and Features
2.1. Clock Networks Architecture and Features x
2.1.1. Clock Network Architecture 2.1.2. Clock Resources 2.1.3. Clock Control Features
2.1.1. Clock Network Architecture x
2.1.1.1. Clock Network Hierarchy 2.1.1.2. Clock Sectors 2.1.1.3. Programmable Clock Routing
2.1.3. Clock Control Features x
2.1.3.1. Clock Gating 2.1.3.2. Clock Divider
2.1.3.1. Clock Gating x
2.1.3.1.1. Root Clock Gate 2.1.3.1.2. Sector Clock Gate 2.1.3.1.3. I/O PLL Clock Gate 2.1.3.1.4. LAB Clock Gate
2.2. PLLs Architecture and Features x
2.2.1. PLL Features 2.2.2. PLL Usage 2.2.3. PLL Locations 2.2.4. PLL Architecture 2.2.5. PLL Control Signals 2.2.6. PLL Feedback Modes 2.2.7. Clock Multiplication and Division 2.2.8. Programmable Phase Shift 2.2.9. Programmable Duty Cycle 2.2.10. PLL Cascading 2.2.11. PLL Input Clock Switchover 2.2.12. PLL Reconfiguration and Dynamic Phase Shift 2.2.13. PLL Calibration
2.2.5. PLL Control Signals x
2.2.5.1. Reset 2.2.5.2. Locked
2.2.6. PLL Feedback Modes x
2.2.6.1. Direct Compensation Mode 2.2.6.2. LVDS Compensation Mode 2.2.6.3. Source Synchronous Compensation Mode 2.2.6.4. Normal Compensation Mode 2.2.6.5. Zero-Delay Buffer Mode 2.2.6.6. External Feedback Mode
2.2.11. PLL Input Clock Switchover x
2.2.11.1. Automatic Switchover 2.2.11.2. Automatic Switchover with Manual Override 2.2.11.3. Manual Clock Switchover
2.2.13. PLL Calibration x
2.2.13.1. Power-Up Calibration 2.2.13.2. User Calibration
3. Intel® Agilex™ Clocking and PLL Design Considerations x
3.1. Guidelines: Clock Switchover 3.2. Guidelines: Timing Closure 3.3. Guidelines: Resetting the PLL 3.4. Guidelines: Configuration Constraints 3.5. Guidelines: I/O PLL Reconfiguration 3.6. Clocking Constraints 3.7. IP Core Constraints 3.8. Guideline: Achieving 5% Duty Cycle for fOUT_EXT ≥ 300 MHz Using tx_outclk Port from LVDS SERDES Intel® FPGA IP
4. Clock Control Intel® FPGA IP Core x
4.1. Release Information for Clock Control Intel® FPGA IP 4.2. Clock Control IP Core Parameters 4.3. Clock Control IP Core Ports and Signals
5. IOPLL Intel® FPGA IP Core x
5.1. Release Information for IOPLL Intel® FPGA IP 5.2. .mif File Generation 5.3. IP-XACT File Generation 5.4. IOPLL IP Core Parameters 5.5. IOPLL IP Core Ports and Signals
5.2. .mif File Generation x
5.2.1. Generating a New .mif File 5.2.2. Adding Configurations to Existing .mif File
5.3. IP-XACT File Generation x
5.3.1. Generating a New IP-XACT File
5.4. IOPLL IP Core Parameters x
5.4.1. IOPLL IP Core Parameters - PLL Tab 5.4.2. IOPLL IP Core Parameters - Settings Tab 5.4.3. IOPLL IP Core Parameters - Cascading Tab 5.4.4. IOPLL IP Core Parameters - Dynamic Reconfiguration Tab 5.4.5. IOPLL IP Core Parameters - Advanced Parameters Tab
6. IOPLL Reconfig Intel® FPGA IP Core x
6.1. Release Information for IOPLL Reconfig Intel® FPGA IP 6.2. Implementing I/O PLL Reconfiguration in the IOPLL Reconfig IP Core 6.3. IOPLL Reconfig IP Core Reconfiguration Modes 6.4. Avalon® Memory-Mapped Interface Ports in the IOPLL Reconfig IP Core 6.5. Address Bus and Data Bus Settings 6.6. Design Example
6.2. Implementing I/O PLL Reconfiguration in the IOPLL Reconfig IP Core x
6.2.1. Connectivity between the IOPLL and IOPLL Reconfig IP Cores 6.2.2. Connecting the IOPLL and IOPLL Reconfig IP Cores
6.3. IOPLL Reconfig IP Core Reconfiguration Modes x
6.3.1. .mif Streaming Reconfiguration 6.3.2. Advanced Mode Reconfiguration 6.3.3. Clock Gating Reconfiguration 6.3.4. Dynamic Phase Shift Reconfiguration
6.3.1. .mif Streaming Reconfiguration x
6.3.1.1. Recalibration Using .mif
6.3.2. Advanced Mode Reconfiguration x
6.3.2.1. Recalibration Using Advanced Mode
6.5. Address Bus and Data Bus Settings x
6.5.1. Address Bus and Data Bus Settings for Advanced Mode Reconfiguration 6.5.2. Output Clock and the Corresponding Data Bit Setting for Clock Gating Reconfiguration 6.5.3. Data Bus Setting for Dynamic Phase Shift for IOPLL Reconfig IP Core
6.5.1. Address Bus and Data Bus Settings for Advanced Mode Reconfiguration x
6.5.1.1. Data Bus Setting for Bandwidth Control and Charge Pump 6.5.1.2. Data Bus Setting for Ripplecap
6.6. Design Example x
6.6.1. Reconfiguration Option: .mif Streaming Reconfiguration Using IOPLL Reconfig IP Core 6.6.2. Reconfiguration Option: Advanced Mode Reconfiguration and Recalibration Using IOPLL Reconfig IP Core 6.6.3. Reconfiguration Option: Clock Gating Reconfiguration Using IOPLL Reconfig IP Core
1. Intel® Agilex™ Clocking and PLL Overview
2. Intel® Agilex™ Clocking and PLL Architecture and Features
3. Intel® Agilex™ Clocking and PLL Design Considerations
4. Clock Control Intel® FPGA IP Core
5. IOPLL Intel® FPGA IP Core
6. IOPLL Reconfig Intel® FPGA IP Core
7. Intel® Agilex™ Clocking and PLL User Guide Archives
8. Document Revision History for the Intel® Agilex™ Clocking and PLL User Guide

5.4.2. IOPLL IP Core Parameters - Settings Tab

Table 9.   IOPLL IP Core Parameters - Settings Tab for Intel® Agilex™ Devices
Parameter Value Description
PLL Bandwidth Preset Low 10, Medium, or High Specifies the PLL bandwidth preset setting. The default selection is Medium for fabric-feeding I/O PLL, and Low for I/O bank I/O PLL.
Lock Threshold Setting Low Lock Time, Medium Lock Time, or High Lock Time

This setting determines the sensitivity of the I/O PLL when detecting lock. This is a tradeoff between the time it takes to lock and the accuracy of the outclk frequency when locked is first asserted. For applications that require the I/O PLL to lock quickly, Low Lock Time is the best option.

The estimated lock times are 30 µs + a × refclk_period, where a is 100, 2048, and 4095 for Low Lock Time, Medium Lock Time, and High Lock Time respectively.

PLL Auto Reset On or Off Automatically self-resets the PLL on loss of lock.
Create a second input clk ‘refclk1’ On or Off Turn on to provide a backup clock attached to your PLL that can switch with your original reference clock.
Second Reference Clock Frequency 11 — Selects the frequency of the second input clock signal. The default value is 100.0 MHz. The minimum and maximum value is dependent on the device used.
Create an ‘active_clk’ signal to indicate the input clock in use 11 On or Off Turn on to create the activeclk output. The activeclk output indicates the input clock which is in use by the PLL. Output signal low indicates refclk and output signal high indicates refclk1.
Create a ‘clkbad’ signal for each of the input clocks 11 On or Off Turn on to create two clkbad outputs, one for each input clock. Output signal low indicates the clock is working and output signal high indicates the clock is not working.
Switchover Mode 11 Automatic Switchover, Manual Switchover, or Automatic Switchover with Manual Override Specifies the switchover mode for design application. The IP supports three switchover modes:
  • If you select the Automatic Switchover mode, the PLL circuitry monitors the selected reference clock. If one clock stops, the circuit automatically switches to the backup clock in a few clock cycles and updates the status signals, clkbad and activeclk.
  • If you select the Manual Switchover mode, when the control signal, extswitch, changes from logic high to logic low, and stays low for at least three clock cycles, the input clock switches to the other clock. The extswitch can be generated from FPGA core logic or input pin.
  • If you select Automatic Switchover with Manual Override mode, when the extswitch signal is high, it overrides the automatic switch function. As long as extswitch remains high, further switchover action is blocked. To select this mode, your two clock sources must be running and the frequency of the two clocks cannot differ by more than 20%. If both clocks are not on the same frequency, but their period difference is within 20%, the clock loss detection block detects the lost clock. The PLL most likely drops out of lock after the PLL clock input switchover and needs time to lock again.
Switchover Delay 11 0–7 Adds a specific amount of cycle delay to the switchover process.
Access to PLL LVDS_CLK/LOADEN output port 10 Disabled, Enable LVDS_CLK/LOADEN 0, or Enable LVDS_CLK/LOADEN 0 & 1 Select Enable LVDS_CLK/LOADEN 0 or Enable LVDS_CLK/LOADEN o & 1 to enable the PLL lvds_clk or loaden output port.

Enables this parameter in case the PLL feeds an LVDS SERDES block with external PLL.

When using the I/O PLL outclk ports with LVDS ports, outclk[0..3] are used for lvds_clk[0,1] and loaden[0,1] ports, outclk4 can be used for coreclk ports.

Enable access to the PLL DPA output port 10 On or Off Turn on to enable the PLL DPA output port.
Enable access to PLL external clock output port On or Off Turn on to enable the PLL external clock output port.
Specifies which outclk to be used as extclk_out[0] source C0–C6 (I/O bank) Specifies the outclk port to be used as extclk_out[0] source.
Specifies which outclk to be used as extclk_out[1] source C0–C6 (I/O bank) Specifies the outclk port to be used as extclk_out[1] source.
10 This option is only available when selecting I/O Bank on the IOPLL Type.
11 This parameter is only available when Create a second input clk 'refclk1' is turned on.
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