Intel® Agilex™ Clocking and PLL User Guide

ID 683761
Date 11/09/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

6.2. Implementing I/O PLL Reconfiguration in the IOPLL Reconfig IP Core

You can enable the PLL reconfiguration circuitry for the I/O PLL through the Avalon® memory-mapped interface in the IOPLL Reconfig IP core.