JESD204B Intel® Stratix® 10 FPGA IP Design Example User Guide

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ID 683758
Date 10/14/2022
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Document Table of Contents
Document Table of Contents x
1. JESD204B Intel® Stratix® 10 FPGA IP Design Example User Guide
1. JESD204B Intel® Stratix® 10 FPGA IP Design Example User Guide x
1.1. JESD204B Intel® Stratix® 10 FPGA IP Design Example Quick Start Guide 1.2. Design Example Detailed Description 1.3. JESD204B Intel® Stratix® 10 FPGA IP Design Example User Guide Archives 1.4. Document Revision History for the JESD204B Intel® Stratix® 10 FPGA IP Design Example User Guide
1.1. JESD204B Intel® Stratix® 10 FPGA IP Design Example Quick Start Guide x
1.1.1. Directory Structure 1.1.2. Generating the Design 1.1.3. Simulating the Design 1.1.4. Compiling and Testing the Design
1.1.2. Generating the Design x
1.1.2.1. Design Example Parameters
1.1.4. Compiling and Testing the Design x
1.1.4.1. Board Connectivity 1.1.4.2. Hardware Test for System Console Control Design Example
1.2. Design Example Detailed Description x
1.2.1. Features 1.2.2. Hardware and Software Requirements 1.2.3. Supported Configurations 1.2.4. Presets 1.2.5. Functional Description 1.2.6. Simulation 1.2.7. Design Example Files 1.2.8. Registers 1.2.9. Signals 1.2.10. Customizing the Design Example
1.2.5. Functional Description x
1.2.5.1. Platform Designer System Component 1.2.5.2. Transport Layer 1.2.5.3. Test Pattern Generator 1.2.5.4. Test Pattern Checker 1.2.5.5. Clocking Scheme
1.2.6. Simulation x
1.2.6.1. Testbench
1.2.10. Customizing the Design Example x
1.2.10.1. Modifying the JESD204B IP Core Parameters 1.2.10.2. Changing the Data Rate or Reference Clock Frequency
1. JESD204B Intel® Stratix® 10 FPGA IP Design Example User Guide

1.2.6.1. Testbench

The simulation design-under-test (DUT) is the generated design example which includes a synthesizable pattern generator and checker. The figures below show the testbench block diagram for simplex and duplex options.

Figure 17. Simulation Testbench Block Diagram (Simplex TX or RX)
Note: Both simplex TX and simplex RX design examples generate the same testbench. The testbench instantiates two DUTs: one simplex TX DUT, one simplex RX DUT. The TX serial data output of the simplex TX DUT is connected to the RX serial data input of the simplex RX DUT. The testbench issues separate Avalon® memory-mapped read/write instructions to the simplex TX and simplex RX DUTs respectively.
Figure 18. Simulation Testbench Block Diagram (Duplex)

The simulation flow replaces the JTAG to Avalon® master bridge module in the Platform Designer system of the System Console Control design example with the Avalon® memory-mapped master bus functional model (BFM). This BFM enables a testbench to send Avalon® memory-mapped read/write commands to the design example registers to mimic the functionality of System Console.

The testbench provided in the simulation flow (/testbench/models/tb_top.sv) executes the following steps:

  1. Reset DUT.
  2. Initialize BFM.
  3. Execute Avalon® memory-mapped commands to initialize the DUT in the following mode:
    • Internal serial loopback mode (for duplex option only)
    • Pattern generator/checker set to PRBS pattern
  4. Wait for DUT to initialize to user mode.
  5. Report JESD204B link status.

When simulation ends, the following messages are shown at end.

Table 17.  Simulation Messages and Description
Message Description
Pattern Checker(s): Data error(s) found! Pattern mismatch errors found on the pattern checker
Pattern Checker(s): OK! No errors found on the pattern checker
Pattern Checker(s): No valid data found! No valid data received by pattern checker
JESD204B Tx Core(s): Tx link error(s) found! Link errors reported by JESD204B IP TX
JESD204B Tx Core(s): OK! No link errors reported by JESD204B IP TX
JESD204B Rx Core(s): Rx link error(s) found! Link errors reported by JESD204B IP RX
JESD204B Rx Core(s): OK! No link errors reported by JESD204B IP RX
TESTBENCH_PASSED: SIM PASSED! Overall simulation passed
TESTBENCH_FAILED: SIM FAILED! Overall simulation failed
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