2022.09.16 |
21.3 |
19.2.0 |
- Added Table: Supported JESD204B IP Parameter Configurations (L, M, F Values)
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2021.11.01 |
21.3 |
19.2.0 |
- Updated the JESD204B Intel® Stratix® 10 FPGA IP Design Example Quick Start Guide chapter:
- Added support for QuestaSim* simulator.
- Updated for latest Intel® branding standards.
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2021.06.25 |
21.2 |
19.2.0 |
- Removed support for NCSim in the following tables and topic:
- Table: Directory and File Description
- Table: Supported Simulators
- Table: Design Example Files for Simulation
- Simulating the Design
- Removed incorrectly included L-tile support for Intel® Stratix® 10 GX FPGA Development Kit board.
- Renamed table title Intel® Stratix® 10 GX FPGA Development Kit Board Connectivity for L-Tile and H-Tile Devices to Intel® Stratix® 10 GX FPGA Development Kit Board Connectivity for H-Tile Devices.
- Updated the table description in Figure: Intel® Stratix® 10 GX FPGA Development Kit Clock Control GUI Setting.
- Updated Hardware and Software Requirements.
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2021.01.07 |
20.4 |
19.2.0 |
- Updated the Compiling and Testing the Design and Board Connectivity sections with the latest information for design examples with bonded and non-bonded mode configurations.
- Removed the note in the description for Bonding Mode in Table: Supported JESD204B IP Core Parameter Configurations.
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2020.10.05 |
20.3 |
19.2.0 |
Updated the change in board information for Intel® Stratix® 10 E-tile devices in the Compiling and Testing the Design and Board Connectivity sections. |
2020.09.10 |
20.2 |
19.2.0 |
- Added design example for Intel® Stratix® 10 E-tile devices. The existing design example supports Intel® Stratix® 10 L-tile and H-tile devices. The Intel® Stratix® 10 E-tile design example uses the Intel® Stratix® 10 TX Transceiver Signal Integrity Development Kit.
- Updated the Compiling and Testing the Design, Board Connectivity, and Hardware and Software Requirements to include information about the Intel® Stratix® 10 TX Transceiver Signal Integrity Development Kit.
- Added the following new procedures for Intel® Stratix® 10 E-tile devices in the Hardware Test for System Console Control Design Example section:
- det_etile
- run_load_PMA_configuration
- load_adaptation_PMA_configuration
- Added the following parameters in the Supported Configurations section:
- Transceiver Tile
- Enable Transceiver Dynamic Reconfiguration
- Enable adaptation load soft IP
- Updated the block diagram in the Functional Description section to include information about the Intel® Stratix® 10 E-tile design example.
- Added Platform Designer system block diagram and top level Platform Designer address map in the Platform Designer System Component section for the Intel® Stratix® 10 E-tile design example.
- Added information about the Intel® Stratix® 10 E-tile devices in the Transceiver PHY Reset Controller, Parallel I/O, and Changing the Data Rate or Reference Clock Frequency sections.
- Added a note in the ATX PLL and Clocking Scheme sections that ATX PLL is not applicable for Intel® Stratix® 10 E-tile devices.
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