JESD204B Intel® Stratix® 10 FPGA IP Design Example User Guide

ID 683758
Date 10/14/2022
Public
Document Table of Contents

1.4. Document Revision History for the JESD204B Intel® Stratix® 10 FPGA IP Design Example User Guide

Document Version Intel® Quartus® Prime Version IP Version Changes
2022.09.16 21.3 19.2.0
  • Added Table: Supported JESD204B IP Parameter Configurations (L, M, F Values)
2021.11.01 21.3 19.2.0
  • Updated the JESD204B Intel® Stratix® 10 FPGA IP Design Example Quick Start Guide chapter:
    • Added support for QuestaSim* simulator.
  • Updated for latest Intel® branding standards.
2021.06.25 21.2 19.2.0
  • Removed support for NCSim in the following tables and topic:
    • Table: Directory and File Description
    • Table: Supported Simulators
    • Table: Design Example Files for Simulation
    • Simulating the Design
  • Removed incorrectly included L-tile support for Intel® Stratix® 10 GX FPGA Development Kit board.
  • Renamed table title Intel® Stratix® 10 GX FPGA Development Kit Board Connectivity for L-Tile and H-Tile Devices to Intel® Stratix® 10 GX FPGA Development Kit Board Connectivity for H-Tile Devices.
  • Updated the table description in Figure: Intel® Stratix® 10 GX FPGA Development Kit Clock Control GUI Setting.
  • Updated Hardware and Software Requirements.
2021.01.07 20.4 19.2.0
  • Updated the Compiling and Testing the Design and Board Connectivity sections with the latest information for design examples with bonded and non-bonded mode configurations.
  • Removed the note in the description for Bonding Mode in Table: Supported JESD204B IP Core Parameter Configurations.
2020.10.05 20.3 19.2.0 Updated the change in board information for Intel® Stratix® 10 E-tile devices in the Compiling and Testing the Design and Board Connectivity sections.
2020.09.10 20.2 19.2.0
  • Added design example for Intel® Stratix® 10 E-tile devices. The existing design example supports Intel® Stratix® 10 L-tile and H-tile devices. The Intel® Stratix® 10 E-tile design example uses the Intel® Stratix® 10 TX Transceiver Signal Integrity Development Kit.
  • Updated the Compiling and Testing the Design, Board Connectivity, and Hardware and Software Requirements to include information about the Intel® Stratix® 10 TX Transceiver Signal Integrity Development Kit.
  • Added the following new procedures for Intel® Stratix® 10 E-tile devices in the Hardware Test for System Console Control Design Example section:
    • det_etile
    • run_load_PMA_configuration
    • load_adaptation_PMA_configuration
  • Added the following parameters in the Supported Configurations section:
    • Transceiver Tile
    • Enable Transceiver Dynamic Reconfiguration
    • Enable adaptation load soft IP
  • Updated the block diagram in the Functional Description section to include information about the Intel® Stratix® 10 E-tile design example.
  • Added Platform Designer system block diagram and top level Platform Designer address map in the Platform Designer System Component section for the Intel® Stratix® 10 E-tile design example.
  • Added information about the Intel® Stratix® 10 E-tile devices in the Transceiver PHY Reset Controller, Parallel I/O, and Changing the Data Rate or Reference Clock Frequency sections.
  • Added a note in the ATX PLL and Clocking Scheme sections that ATX PLL is not applicable for Intel® Stratix® 10 E-tile devices.
Document Version Intel® Quartus® Prime Version Changes
2018.12.10 18.1
  • Updated the Enable manual F configuration, F, and N' parameter description in the Supported Configurations section to add information for F=3 configuration.
  • Added an example for calculating frame clock frequency when F=3 for actual frame clock for a serial data rate of 6 Gbps in the Core PLL section.
  • Updated the fTXframe and fRXframe for Different F Parameter Settings table in the Core PLL section to include a row for F=3.
  • Updated the descriptions for avst_usr_din[LINK*TL_DATA_BUS_WIDTH-1:0] and avst_usr_dout[LINK*TL_DATA_BUS_WIDTH-1:0] signals in the System Interface Signals table to include information for F=3.
  • Added a reminder note in the Compiling and Testing the Design section to configure the VID assignments if you are using development boards other than the Intel® Stratix® 10 GX FPGA development board and the Intel® Stratix® 10 GX Transceiver Signal Integrity development board.
  • Edited the duplex variant description in the ATX PLL section. For duplex variant, the ATX PLL and CDR share the same reference clock pin.
  • Edited the description for the Generate HDL Parameter for Synthesis parameter in the Design Example Parameters section.
2018.08.10 18.0
  • Added a note in the Reset Sequencer section that for Intel® Stratix® 10 devices, reset deassertion staggering of TX/RX analog and digital reset happens before the assertion of TX/RX ready.
  • Changed the target development board for the design example from Signal Integrity (SI) development board to FPGA development board.
  • Updated the Intel® Stratix® 10 FPGA Development Kit Board Connectivity table to include the FPGA development board information.
  • Updated the Clock Control GUI Setting figure.
  • Shortened the following Platform Designer file names due to Windows limitation:
    • altera_jesd204_ed_qsys_<data path>.qsys to altjesd_ed_qsys_<data path>.qsys
    • altera_jesd204_subsystem_<data path>.qsys to altjesd_ss_<data path>.qsys
  • Edited the Platform Designer System for System Console Control Design Example figure.
    • Removed signal connections that indicated support for dynamic transceiver reconfiguration. The design example does not support dynamic transceiver reconfiguration.
    • Added that the output from ATX PLL could either be TX serial clock or TX bonding clock.
    • Removed "Core PLL reset" and "JESD204B IP core SerDes PHY reset" from Note 1. These resets are connected internally.
Date Version Changes
November 2017 2017.11.06
  • Added information about simplex and duplex ATX reference clock frequencies.
  • Defined (altera_jesd204_ed_<data path>.sv) as the top level RTL file in Core PLL.
  • Added Frame Clock and Link Clock Relationship subsection.
  • Defined top level RTL file in Changing the Data Rate or Reference Clock Frequency.
  • Updated SDC constraint to be modified in Changing the Data Rate or Reference Clock Frequency.
  • Added get_master_index procedure in Procedures in the main.tcl System Console Script table.
  • Updated document title.
  • Updated instances of Qsys to Platform Designer.
May 2017 2017.05.08
  • Added new directories and descriptions in Directory Structure.
  • Updated steps in Generating the Design.
  • Updated design example parameters and descriptions Design Example Parameters.
  • Added new simulators in Simulating the Design.
  • Updated steps in Compiling and Testing the Design.
  • Added Hardware Test for System Console Control Design Example.
  • Updated the supported configuration in Supported Configurations.
  • Updated preset settings.
  • Updated JESD204B Design Example Block Diagram.
  • Updated descriptions and figures in Platform Designer System Components.
  • Updated System Clocking for the Design Example.
  • Added tx_link_error, rx_link_error, and spi_SDIO signals in System Interface Signals.
  • Updated Testbench.
December 2016 2016.12.09 Initial release.