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1.2.7. Design Example Files
There are two flows for the design example: simulation and synthesis.
Design Example Flow | Directory |
---|---|
Simulation | <your project>/ed_sim |
Synthesis | <your project>/ed_synth |
The following tables list the important folders and files for simulation and synthesis.
File Type | File/Folder | Description |
---|---|---|
Run script files | /testbench/aldec/run_tb_top.tcl | TCL run script for Riviera-PRO* simulator |
/testbench/mentor/run_tb_top.tcl | TCL run script for ModelSim* or QuestaSim* simulator | |
/testbench/synopsys/vcs/run_tb_top.sh | Shell run script for VCS* simulator | |
/testbench/synopsys/vcsmx/run_tb_top.sh | Shell run script for VCS* MX simulator | |
/testbench/xcelium/run_tb_top.sh | Shell run script for Xcelium* simulator | |
Source files | /testbench/models/altjesd_ed_qsys_<data path>.qsys | Top level Platform Designer system project |
/testbench/models/altjesd_ss_<data path>.qsys | JESD204B subsystem Platform Designer system project | |
/testbench/models/ip/ | IP folder containing instantiated IP modules | |
/testbench/models/altera_jesd204_ed_<data path>.sv | Top level HDL | |
/testbench/models/tb_top.sv | Top level testbench | |
/testbench/spi_mosi_oe.v | Output buffer HDL | |
/testbench/switch_debouncer.v | Switch debouncer HDL | |
/testbench/pattern/ | Folder containing the test pattern generator and checker HDL | |
/testbench/transport_layer | Folder containing assembler and de-assembler HDL. |
File Type | File/Folder | Description |
---|---|---|
Intel® Quartus® Prime project files | altera_jesd204_ed_<data path>.qpf | Intel® Quartus® Prime project file |
altera_jesd204_ed_<data path>.qsf | Intel® Quartus® Prime settings file | |
Source files | altera_jesd204_ed_<data path>.sv | Top level HDL |
altera_jesd204_ed_<data path>.sdc | Synopsys* Design Constraints (SDC) file containing all timing/placement constraints | |
transport_layer/ | Folder containing assembler and de-assembler HDL | |
pattern/ | Folder containing the test pattern generator and checker HDL | |
spi_mosi_oe.v | Output buffer HDL | |
switch_debouncer.v | Switch debouncer HDL | |
altjesd_ed_qsys_<data path>.qsys | Top level Platform Designer system project | |
altjesd_ss_<data path>.qsys | JESD204B subsystem Platform Designer system project |