Intel Agilex® 7 JTAG Boundary-Scan Testing User Guide

Download PDF
ID 683748
Date 12/04/2023
Public
Document Table of Contents
Document Table of Contents x
1. Intel Agilex® 7 JTAG BST Overview 2. Intel Agilex® 7 JTAG BST Architecture 3. Intel Agilex® 7 BST Operation Control 4. Intel Agilex® 7 I/O Voltage for JTAG Operation 5. Enabling and Disabling Intel Agilex® 7 BST Circuitry 6. Intel Agilex® 7 BST Guidelines 7. Document Revision History for the Intel Agilex® 7 JTAG Boundary-Scan Testing User Guide
2. Intel Agilex® 7 JTAG BST Architecture x
2.1. JTAG Circuitry Functional Model 2.2. JTAG Pins 2.3. IEEE Std. 1149.1 Boundary-Scan Register 2.4. IEEE Std. 1149.6 Boundary-Scan Register
2.3. IEEE Std. 1149.1 Boundary-Scan Register x
2.3.1. Boundary-Scan Cells of Intel Agilex® 7 Device I/O Pin
3. Intel Agilex® 7 BST Operation Control x
3.1. Device ID 3.2. Supported JTAG Instructions
5. Enabling and Disabling Intel Agilex® 7 BST Circuitry x
5.1. Enabling BST Circuitry 5.2. Disabling BST Circuitry
6. Intel Agilex® 7 BST Guidelines x
6.1. Performing Intel Agilex® 7 Boundary-Scan Testing 6.2. Intel Agilex® 7 IEEE Std. 1149.1 BST Guidelines
1. Intel Agilex® 7 JTAG BST Overview
2. Intel Agilex® 7 JTAG BST Architecture
3. Intel Agilex® 7 BST Operation Control
4. Intel Agilex® 7 I/O Voltage for JTAG Operation
5. Enabling and Disabling Intel Agilex® 7 BST Circuitry
6. Intel Agilex® 7 BST Guidelines
7. Document Revision History for the Intel Agilex® 7 JTAG Boundary-Scan Testing User Guide

6.2. Intel Agilex® 7 IEEE Std. 1149.1 BST Guidelines

Consider the following guidelines when you perform BST with IEEE Std. 1149.1 devices:

  • If the first two bits shifted out of the instruction register in the SHIFT_IR state are not 1 and then 0, the TAP controller did not reach the proper state. To solve this problem, try one of the following procedures:
    • Verify that the TAP controller has reached the SHIFT_IR state correctly. To advance the TAP controller to the SHIFT_IR state, return to the TEST-LOGIC-RESET state and send the 01100 code to the TMS pin.
    • Check the connections to the VCC, GND, JTAG, and dedicated configuration pins on the device.
  • Perform a SAMPLE/PRELOAD test cycle before the first EXTEST test cycle to ensure that known data is present at the device pins when you enter EXTEST mode. If the OEJ update register contains 0, the data in the OUTJ update register is driven out. The state must be known and correct to avoid contention with other devices in the system.
  • Do not perform EXTEST testing during in-circuit reconfiguration because EXTEST is not supported during in-circuit reconfiguration.
  • After configuration, you cannot test any pins in a differential pin pair. To perform BST after configuration, edit and redefine the BSC group that correspond to these differential pin pairs as an internal cell.
Level Two Title