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1. Intel Agilex® 7 JTAG BST Overview
2. Intel Agilex® 7 JTAG BST Architecture
3. Intel Agilex® 7 BST Operation Control
4. Intel Agilex® 7 I/O Voltage for JTAG Operation
5. Enabling and Disabling Intel Agilex® 7 BST Circuitry
6. Intel Agilex® 7 BST Guidelines
7. Document Revision History for the Intel Agilex® 7 JTAG Boundary-Scan Testing User Guide
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5.1. Enabling BST Circuitry
The IEEE Std. 1149.1 BST circuitry is enabled after the device is configured. If you need to perform the boundary-scan test prior to configuration, you must execute the MISCCTRL instruction upon device power up to enable the BST circuitry.
MISCCTRL Instruction for Intel Agilex® 7 R-Tile Devices
!Shift 10-bit MISCCTRL instruction (0x013) to Instruction Register SIR 10 TDI (013); !Transition to Run-Test-Idle state STATE IDLE; !Shift 8-bit data (0x47) to Data Register for BST circuitry enabling SDR 8 TDI (47);
MISCCTRL Instruction for All Other Devices
!Shift 10-bit MISCCTRL instruction (0x013) to Instruction Register SIR 10 TDI (013); !Transition to Run-Test-Idle state STATE IDLE; !Shift 8-bit data (0x01) to Data Register for BST circuitry enabling SDR 8 TDI (01);