Agilex® 7 JTAG Boundary-Scan Testing User Guide

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ID 683748
Date 11/04/2024
Public
Document Table of Contents
Document Table of Contents x
1. Agilex® 7 JTAG BST Overview 2. Agilex® 7 JTAG BST Architecture 3. Agilex® 7 BST Operation Control 4. Agilex® 7 I/O Voltage for JTAG Operation 5. Enabling and Disabling Agilex® 7 BST Circuitry 6. Agilex® 7 BST Guidelines 7. Document Revision History for the Agilex® 7 JTAG Boundary-Scan Testing User Guide
2. Agilex® 7 JTAG BST Architecture x
2.1. JTAG Circuitry Functional Model 2.2. JTAG Pins 2.3. IEEE Std. 1149.1 Boundary-Scan Register 2.4. IEEE Std. 1149.6 Boundary-Scan Register
2.3. IEEE Std. 1149.1 Boundary-Scan Register x
2.3.1. Boundary-Scan Cells of Agilex® 7 Device I/O Pin
3. Agilex® 7 BST Operation Control x
3.1. Device ID 3.2. Supported JTAG Instructions
5. Enabling and Disabling Agilex® 7 BST Circuitry x
5.1. Enabling BST Circuitry 5.2. Disabling BST Circuitry
6. Agilex® 7 BST Guidelines x
6.1. Performing Agilex® 7 Boundary-Scan Testing 6.2. Agilex® 7 IEEE Std. 1149.1 BST Guidelines
1. Agilex® 7 JTAG BST Overview
2. Agilex® 7 JTAG BST Architecture
3. Agilex® 7 BST Operation Control
4. Agilex® 7 I/O Voltage for JTAG Operation
5. Enabling and Disabling Agilex® 7 BST Circuitry
6. Agilex® 7 BST Guidelines
7. Document Revision History for the Agilex® 7 JTAG Boundary-Scan Testing User Guide

5.2. Disabling BST Circuitry

To esue that you do ot iadvetetly eable the IEEE Std. 1149.1 cicuity whe it is ot equied, disable the cicuity pemaetly with pi coectios as listed i the followig table.

Table 8.  Pi Coectios to Pemaetly Disable the IEEE Std. 1149.1 Cicuity fo Agilex® 7 Devices
JTAG Pis3 Coectio fo Disablig
TMS VCCIO_SDM
TCK GND
TDI VCCIO_SDM
TDO Leave ope
3 The JTAG pis ae dedicated. Softwae optio is ot available to disable JTAG i Agilex® 7 devices.
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