Intel Agilex® 7 JTAG Boundary-Scan Testing User Guide

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ID 683748
Date 12/04/2023
Public
Document Table of Contents
Document Table of Contents x
1. Intel Agilex® 7 JTAG BST Overview 2. Intel Agilex® 7 JTAG BST Architecture 3. Intel Agilex® 7 BST Operation Control 4. Intel Agilex® 7 I/O Voltage for JTAG Operation 5. Enabling and Disabling Intel Agilex® 7 BST Circuitry 6. Intel Agilex® 7 BST Guidelines 7. Document Revision History for the Intel Agilex® 7 JTAG Boundary-Scan Testing User Guide
2. Intel Agilex® 7 JTAG BST Architecture x
2.1. JTAG Circuitry Functional Model 2.2. JTAG Pins 2.3. IEEE Std. 1149.1 Boundary-Scan Register 2.4. IEEE Std. 1149.6 Boundary-Scan Register
2.3. IEEE Std. 1149.1 Boundary-Scan Register x
2.3.1. Boundary-Scan Cells of Intel Agilex® 7 Device I/O Pin
3. Intel Agilex® 7 BST Operation Control x
3.1. Device ID 3.2. Supported JTAG Instructions
5. Enabling and Disabling Intel Agilex® 7 BST Circuitry x
5.1. Enabling BST Circuitry 5.2. Disabling BST Circuitry
6. Intel Agilex® 7 BST Guidelines x
6.1. Performing Intel Agilex® 7 Boundary-Scan Testing 6.2. Intel Agilex® 7 IEEE Std. 1149.1 BST Guidelines
1. Intel Agilex® 7 JTAG BST Overview
2. Intel Agilex® 7 JTAG BST Architecture
3. Intel Agilex® 7 BST Operation Control
4. Intel Agilex® 7 I/O Voltage for JTAG Operation
5. Enabling and Disabling Intel Agilex® 7 BST Circuitry
6. Intel Agilex® 7 BST Guidelines
7. Document Revision History for the Intel Agilex® 7 JTAG Boundary-Scan Testing User Guide

1. Intel Agilex® 7 JTAG BST Overview

Intel Agilex® 7 devices support IEEE Std. 1149.1 BST and IEEE Std. 1149.6 BST. When you perform Boundary-Scan Test (BST), you can test pin connections without using physical test probes and capture functional data during normal operation. The boundary-scan cells (BSCs) in a device can force signals onto pins, or capture data from pin or core logic signals. Forced test data is serially shifted into the BSCs. Captured data is serially shifted out and externally compared to expected results.

Intel Agilex® 7 devices are implemented using multiple die inside the package, connected together using EMIB (Embedded Multi-die Interconnect Bridge) technology. The multiple die implementation is transparent to BST. There is a single boundary-scan chain for the complete device that includes every die inside the package.

You can perform BST on Intel Agilex® 7 devices before, after, and during configuration.

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