Turbo Intel® FPGA IP User Guide

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ID 683734
Date 9/30/2021
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Document Table of Contents
Document Table of Contents x
1. About the Turbo Intel® FPGA IP 2. Getting Started with the Turbo Intel® FPGA IP 3. Parameter Settings 4. Turbo Intel® FPGA IP Functional Description A. Turbo IP Core User Guide Document Archives 5. Document Revision History for Turbo Intel® FPGA IP User Guide
1. About the Turbo Intel® FPGA IP x
1.1. Turbo Intel® FPGA IP Features 1.2. Turbo Intel® FPGA IP Device Family Support 1.3. Turbo IP Core Performance and Resource Utilization 1.4. Turbo Code Licensing Disclaimer 1.5. Release Information
2. Getting Started with the Turbo Intel® FPGA IP x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. IP Catalog and Parameter Editor 2.3. Specifying the IP Core Parameters and Options 2.4. Simulating Intel® FPGA IP Cores 2.5. Simulating the Turbo IP with the RTL Simulator 2.6. Simulating the Turbo IP with the C-Model 2.7. Simulating the Turbo IP with MATLAB
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode 2.1.2. Turbo IP Timeout Behavior
2.3. Specifying the IP Core Parameters and Options x
2.3.1. IP Core Generation Output ( Intel® Quartus® Prime Pro Edition)
2.6. Simulating the Turbo IP with the C-Model x
2.6.1. Encoder Simulation 2.6.2. Decoder Simulation
4. Turbo Intel® FPGA IP Functional Description x
4.1. Turbo Encoder 4.2. Turbo Decoder 4.3. 4.4. Turbo Throughput
4.1. Turbo Encoder x
4.1.1. Turbo Encoder Data Format 4.1.2. Turbo Encoder Latency Calculation
4.2. Turbo Decoder x
4.2.1. Turbo Decoder Data Format 4.2.2. CRC24A or CRC24B Early Termination 4.2.3. Decoder Latency Calculation 4.2.4. Error Correction Performance for the Turbo Decoder
4.3. x
4.3.1. Packet Format Errors
1. About the Turbo Intel® FPGA IP
2. Getting Started with the Turbo Intel® FPGA IP
3. Parameter Settings
4. Turbo Intel® FPGA IP Functional Description
A. Turbo IP Core User Guide Document Archives
5. Document Revision History for Turbo Intel® FPGA IP User Guide

1.3. Turbo IP Core Performance and Resource Utilization

Table 2.  Performance and Resource UtilizationTypical expected performance for a Turbo IP Core using the Quartus Prime software with the Intel® Agilex™ (AGFA014R24A2E2VR0), Intel® Stratix® 10 (1SG280HU2F50E2VG), and Intel® Arria® 10 (10AT115S1F45E1SG) devices.
Device Speed Grade Parameters ALM Memory fMAX1 (MHz)
Codec Type Standard Input Bits Engines M20K M10K
Intel® Agilex™ 2 Encoder LTE - 1 529 8 - 425
- 4 900 10 - 425
- 8 1.4K 19 - 425
- - 529 8 - 425
UMTS - 1 1.1K 9 - 432
Decoder LTE 6 8 12.8K 27 - 414
8 8 15.2K 32 - 411
6 16 23.4K 34 - 383
8 16 28K 40 - 365
UMTS 6 2 4.9K 80 - 303
8 2 5.5K 90 - 295
6 4 7.2K 92 - 304
8 4 8.1K 97 - 286
Intel® Stratix® 10 2 Encoder LTE - 1 528 8 - 405
- 4 987 10 - 411
- 8 1.4K 19 - 381
UMTS - 1 1.1K 9 - 330
- 1 1.1K 9 - 315
Decoder LTE 6 8 12.7K 27 - 313
8 8 15.2K 32 - 313
6 16 23.2K 34 - 292
8 16 27.8K 40 - 271
UMTS 6 2 4.8K 80 - 239
8 2 5.5K 90 - 230
6 4 7.1K 92 - 239
8 4 8.1K 97 - 225
Intel® Arria® 10 1 Encoder LTE - 1 476 2 - 425
- 4 902 10 - 371
- 8 1.4K 10 - 371
UMTS - 1 1K 4 - 304
Decoder LTE 6 8 11K 27 - 323
8 8 13K 32 - 331
6 16 19.9K 34 - 311
8 16 23.8K 40 - 298
UMTS 6 2 4.7K 71 - 228
8 2 5.5K 81 - 213
6 4 7.4K 73 - 225
8 4 8.4K 78 - 208
1 The table shows fMAX frequency reduced by 15%. The actual average is fMAX x 1.15.
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