Turbo Intel® FPGA IP User Guide

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ID 683734
Date 9/30/2021
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Document Table of Contents
Document Table of Contents x
1. About the Turbo Intel® FPGA IP 2. Getting Started with the Turbo Intel® FPGA IP 3. Parameter Settings 4. Turbo Intel® FPGA IP Functional Description A. Turbo IP Core User Guide Document Archives 5. Document Revision History for Turbo Intel® FPGA IP User Guide
1. About the Turbo Intel® FPGA IP x
1.1. Turbo Intel® FPGA IP Features 1.2. Turbo Intel® FPGA IP Device Family Support 1.3. Turbo IP Core Performance and Resource Utilization 1.4. Turbo Code Licensing Disclaimer 1.5. Release Information
2. Getting Started with the Turbo Intel® FPGA IP x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. IP Catalog and Parameter Editor 2.3. Specifying the IP Core Parameters and Options 2.4. Simulating Intel® FPGA IP Cores 2.5. Simulating the Turbo IP with the RTL Simulator 2.6. Simulating the Turbo IP with the C-Model 2.7. Simulating the Turbo IP with MATLAB
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode 2.1.2. Turbo IP Timeout Behavior
2.3. Specifying the IP Core Parameters and Options x
2.3.1. IP Core Generation Output ( Intel® Quartus® Prime Pro Edition)
2.6. Simulating the Turbo IP with the C-Model x
2.6.1. Encoder Simulation 2.6.2. Decoder Simulation
4. Turbo Intel® FPGA IP Functional Description x
4.1. Turbo Encoder 4.2. Turbo Decoder 4.3. 4.4. Turbo Throughput
4.1. Turbo Encoder x
4.1.1. Turbo Encoder Data Format 4.1.2. Turbo Encoder Latency Calculation
4.2. Turbo Decoder x
4.2.1. Turbo Decoder Data Format 4.2.2. CRC24A or CRC24B Early Termination 4.2.3. Decoder Latency Calculation 4.2.4. Error Correction Performance for the Turbo Decoder
4.3. x
4.3.1. Packet Format Errors
1. About the Turbo Intel® FPGA IP
2. Getting Started with the Turbo Intel® FPGA IP
3. Parameter Settings
4. Turbo Intel® FPGA IP Functional Description
A. Turbo IP Core User Guide Document Archives
5. Document Revision History for Turbo Intel® FPGA IP User Guide

4.1. Turbo Encoder

The 3GPP Turbo encoder uses a parallel concatenated convolutional code. A convolutional encoder encodes an information sequence and another convolutional encoder encodes an interleaved version of the information sequence. The Turbo encoder has two 8-state constituent encoders and one Turbo code internal interleaver. The Turbo encoder accepts K bits and outputs 3K+12 bits, having a natural code rate 1/3. The last 12 output bits of every packet are termination bits, which guarantee that the state of the encoder is back to state zero in the end of encoding process.
Figure 6. Turbo Encoder Block Diagram

The output from the turbo coder is:

X 0, Z 0, Z’ 0, X 1, Z 1, Z’ 1, ..., X K–1, Z K–1, Z’ K–1

Where:

  • Bits X 0, X 1, ..., X K–1 are input to both the first 8-state constituent encoder and the internal interleaver (K is the number of bits).
  • Bits Z 0, Z 1, ..., Z K–1 and Z’ 0, Z’ 1, ..., Z’ K–1 are output from the first and second 8-state constituent encoders.
  • The bits output from the internal interleaver (and input to the second 8-state constituent encoder) are X’ 0, X’ 1, ..., X’ K–1.
  • Additionally, encoder outputs 12 termination bits, X K , X K+1, X K+2, X’ K, X’ K+1, X’ K+2, Z K, Z K+1, Z K+2, Z’ K, Z’ K+1, Z’ K+2.
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