1.2.1. Managing Uncontrolled Loss of Power Events
Sudden loss of power events such as a utility grid blackout, accidental removal of the system power cable, or other uncontrolled loss of power events can create difficult power management scenarios for the system designer. To manage these types of exceptions, ensure the power management design incorporates these features:
- Loss of power detection
- Hold-up capacitor (if needed) to keep the Power Management Circuitry operational during shutdown
- Reset logic to the FPGA and system to minimize power consumption during shutdown
- Rapid discharge circuit for each power group to minimize power-down time
Figure 6. Fault Tolerant Block Diagram
The following figure shows a conceptual implementation for managing uncontrolled power loss events.
The Power Management Circuit (in the above diagram) is powered directly from the VIN high-side DC input voltage (for example, 12 V or higher) but can operate down to a lower voltage such as 5 V. You may need CHOLD to maintain sufficient charge to keep the Power Management Circuitry operational during loss of power events. CDECAP Group 1-3 represents the total decoupling capacitance associated with each power rail grouping. RDISCHARGE 2-3 and its associated power FETs enable fast discharging of each power group voltage to 0 V when you initiate a shutdown sequence. The fast discharging circuit speeds up the power-down cycle of each rail (as the natural RC discharge decay can be very slow) and can also define the order in which the rails discharge by trimming RDISCHARGE. Without the fast discharge circuit, the shutdown time can be very long, requiring a larger capacitance for CHOLD.
Theory of Operation
While the system is running, the high-side DC input is maintained at VIN +/-10% tolerance. The power loss detection circuit continuously monitors the DC input for a loss of power event. This detection circuit can be a simple comparator with a reference voltage set to a threshold slightly below the -10% threshold, or it can be an Analog-to-Digital Converter (ADC) employing multiple successive samplings to discriminate against false power interruptions.
When a valid loss of power event occurs, the detection circuit generates a reset to the Voltage Controller and the FPGA. It is the user's responsibility to use the reset signal to reset as much of the design as possible in order to reduce dynamic power and the operational current of the FPGA by putting it into a low Static Power (Pstatic) state. Concurrently, the Power Management Circuit is triggered to initiate a shutdown sequence. This reduces the value of CHOLD needed to support the Power Management Circuitry during the shutdown process.
Note: The Voltage Monitor generated reset signal and the reset IP signal should be tied to the same reset distribution. This helps in resetting the PLLs and additional power reduction. Refer to the AN 891: Using the Reset Release Stratix® 10 FPGA IP for more details on Stratix® 10 Reset IP.
Figure 7. Main Power Loss Detection and Shutdown Event
The ∆t time that the Power Management Circuit has to perform a graceful power-down is dependent on the total power consumption of the system and CHOLD capacitor needed to maintain reliable system power. While the individual power groups are being disabled in reverse sequential order, the FET for each particular group is also successively turned on to facilitate a rapid discharge of their respective power rail to ground through the RDISCHARGE resistors. You must properly size the discharge FET and resistor to handle the instantaneous discharge current through it. The discharge resistor must be able to handle the single pulse power load for the duration of the discharge time. You can determine this from the data sheet of the selected resistor. The data sheet typically provides this data as a graph plotting the Maximum pulse load power versus the Pulse duration for various resistor package sizes. Determine the value of CHOLD from the energy stored in the capacitor and the total power required to maintain system operation, calculated from the following equations:
E = Energy stored in the capacitor in Joules
P = Power in Watts
V = Voltage in Volts
C = Capacitance in Farads
t = Time in Seconds
Eff = Efficiency percentage of the regulator
Example Design
Consider an FPGA system that has total quiescent current of 25 A when the system is under reset (FPGA leakage and total system standby current), and the hold time of the capacitor needs to be 1 ms as the voltage drops from 10 V to 5 V. Also, assume that the voltage rail is 0.9 V.
Determine the CHOLD capacitance required for the Power Management Controller to maintain operation so that you can complete a proper power-down sequence.
From the above equation:
CHOLD = (2 * 25 A * 0.9 V * .001 s) / (0.85 * (10^2 -5^2))
= 0.045 / 63.75 µF
= 706 µF