AN 692: Power Sequencing Considerations for Cyclone® 10 GX, Arria® 10, Stratix® 10, Agilex™ 7, and Agilex™ 5 Devices

ID 683725
Date 9/26/2024
Public

1.3.3. 3VIO Pin Guidance for Unpowered FPGA

For the unpowered FPGA, the 3VIO must be in tristate during power-up and power-down. This pin can be in tristate or clamp to GND.