Visible to Intel only — GUID: rhy1670347514283
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1.3.3. 3VIO Pin Guidance for Unpowered FPGA
For the unpowered FPGA, the 3VIO must be in tristate during power-up and power-down. This pin can be in tristate or clamp to GND.
Visible to Intel only — GUID: rhy1670347514283
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