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1. Datasheet
2. Quick Start Guide
3. Parameter Settings
4. Physical Layout
5. 64- or 128-Bit Avalon-MM Interface to the Endpoint Application Layer
6. Registers
7. Reset and Clocks
8. Interrupts for Endpoints
9. Error Handling
10. Design Implementation
11. Throughput Optimization
12. Additional Features
13. Avalon-MM Testbench and Design Example
14. Avalon-MM Testbench and Design Example for Root Port
15. Hard IP Reconfiguration
16. Debugging
A. PCI Express Protocol Stack
B. Transaction Layer Packet (TLP) Header Formats
C. Lane Initialization and Reversal
D. Arria® 10 or Cyclone® 10 GX Avalon® -MM Interface for PCIe* Solutions User Guide Archive
E. Document Revision History
1.1. Arria® 10 or Cyclone® 10 GX Avalon-MM Interface for PCIe Datasheet
1.2. Features
1.3. Release Information
1.4. Device Family Support
1.5. Configurations
1.6. Design Examples
1.7. IP Core Verification
1.8. Resource Utilization
1.9. Recommended Speed Grades
1.10. Creating a Design for PCI Express
3.1. Parameters
3.2. Avalon-MM Settings
3.3. Base Address Register (BAR) Settings
3.4. Device Identification Registers
3.5. PCI Express and PCI Capabilities Parameters
3.6. Configuration, Debug, and Extension Options
3.7. Vendor Specific Extended Capability (VSEC)
3.8. PHY Characteristics
3.9. Example Designs
5.1. 32-Bit Non-Bursting Avalon-MM Control Register Access (CRA) Slave Signals
5.2. Bursting and Non-Bursting Avalon® -MM Module Signals
5.3. 64- or 128-Bit Bursting TX Avalon-MM Slave Signals
5.4. Clock Signals
5.5. Reset, Status, and Link Training Signals
5.6. Interrupts for Endpoints when Multiple MSI/MSI-X Support Is Enabled
5.7. Hard IP Status Signals
5.8. Physical Layer Interface Signals
6.1. Correspondence between Configuration Space Registers and the PCIe Specification
6.2. Type 0 Configuration Space Registers
6.3. Type 1 Configuration Space Registers
6.4. PCI Express Capability Structures
6.5. Intel-Defined VSEC Registers
6.6. CvP Registers
6.7. 64- or 128-Bit Avalon-MM Bridge Register Descriptions
6.8. Programming Model for Avalon-MM Root Port
6.9. Uncorrectable Internal Error Mask Register
6.10. Uncorrectable Internal Error Status Register
6.11. Correctable Internal Error Mask Register
6.12. Correctable Internal Error Status Register
6.7.1.1. Avalon-MM to PCI Express Interrupt Status Registers
6.7.1.2. Avalon-MM to PCI Express Interrupt Enable Registers
6.7.1.3. PCI Express Mailbox Registers
6.7.1.4. Avalon-MM-to-PCI Express Address Translation Table
6.7.1.5. PCI Express to Avalon-MM Interrupt Status and Enable Registers for Endpoints
6.7.1.6. Avalon-MM Mailbox Registers
6.7.1.7. Control Register Access (CRA) Avalon-MM Slave Port
13.5.1. ebfm_barwr Procedure
13.5.2. ebfm_barwr_imm Procedure
13.5.3. ebfm_barrd_wait Procedure
13.5.4. ebfm_barrd_nowt Procedure
13.5.5. ebfm_cfgwr_imm_wait Procedure
13.5.6. ebfm_cfgwr_imm_nowt Procedure
13.5.7. ebfm_cfgrd_wait Procedure
13.5.8. ebfm_cfgrd_nowt Procedure
13.5.9. BFM Configuration Procedures
13.5.10. BFM Shared Memory Access Procedures
13.5.11. BFM Log and Message Procedures
13.5.12. Verilog HDL Formatting Functions
A.4.1. Avalon‑MM Bridge TLPs
A.4.2. Avalon-MM-to-PCI Express Write Requests
A.4.3. Avalon-MM-to-PCI Express Upstream Read Requests
A.4.4. PCI Express-to-Avalon-MM Read Completions
A.4.5. PCI Express-to-Avalon-MM Downstream Write Requests
A.4.6. PCI Express-to-Avalon-MM Downstream Read Requests
A.4.7. Avalon-MM-to-PCI Express Read Completions
A.4.8. PCI Express-to-Avalon-MM Address Translation for 32-Bit Bridge
A.4.9. Minimizing BAR Sizes and the PCIe Address Space
A.4.10. Avalon® -MM-to-PCI Express Address Translation Algorithm for 32-Bit Addressing
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13.4.1. Root Port BFM Overview
The basic Root Port BFM provides Verilog HDL task‑based interface to request transactions to issue on the PCI Express link. The Root Port BFM also handles requests received from the PCI Express link. The following figure shows the most important modules in the Root Port BFM.
Figure 58. Root Port BFM
These modules implement the following functionality:
- BFM Log Interface,altpcietb_bfm_log.v and altlpcietb_bfm_rp_<gen>_x8.v: The BFM log functions provides routine for writing commonly formatted messages to the simulator standard output and optionally to a log file. It also provides controls that stop simulation on errors. For details on these procedures, refer to BFM Log and Message Procedures.
- BFM Read/Write Request Functions, altpcietb_bfm_rp_<gen>_x8.sv: These functions provide the basic BFM calls for PCI Express read and write requests. For details on these procedures, refer to BFM Read and Write Procedures.
- BFM Log Interface, altpcietb_bfm_log.v and altlpcietb_bfm_rp_<gen>_x8.v: The BFM log functions provides routine for writing commonly formatted messages to the simulator standard output and optionally to a log file. It also provides controls that stop simulation on errors. For details on these procedures, refer to BFM Log and Message Procedures.
- BFM Configuration Functions, altpcietb_g3bfm_configure.v : These functions provide the BFM calls to request configuration of the PCI Express link and the Endpoint Configuration Space registers. For details on these procedures and functions, refer to BFM Configuration Procedures.
- BFM shared memory, altpcietb_g3bfm_shmem_common.v: This modules provides the Root Port BFM shared memory. It implements the following functionality:
- Provides data for TX write operations
- Provides data for RX read operations
- Receives data for RX write operations
- Receives data for received completions
- BFM Request Interface, altpcietb_g3bfm_req_intf.v: This interface provides the low-level interface between the altpcietb_g3bfm_rdwr and altpcietb_bfm_configure procedures or functions and the Root Port RTL Model. This interface stores a write-protected data structure containing the sizes and the values programmed in the BAR registers of the Endpoint. It also stores other critical data used for internal BFM management. You do not need to access these files directly to adapt the testbench to test your Endpoint application.
- Avalon‑ST Interfaces, altpcietb_g3bfm_vc_intf_ast_common.v: These interface modules handle the Root Port interface model. They take requests from the BFM request interface and generate the required PCI Express transactions. They handle completions received from the PCI Express link and notify the BFM request interface when requests are complete. Additionally, they handle any requests received from the PCI Express link, and store or fetch data from the shared memory before generating the required completions.