Arria® 10 and Cyclone® 10 GX Avalon® Memory-Mapped (Avalon-MM) Interface for PCI Express* User Guide

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ID 683724
Date 9/10/2024
Public
Document Table of Contents
Document Table of Contents x
1. Datasheet 2. Quick Start Guide 3. Parameter Settings 4. Physical Layout 5. 64- or 128-Bit Avalon-MM Interface to the Endpoint Application Layer 6. Registers 7. Reset and Clocks 8. Interrupts for Endpoints 9. Error Handling 10. Design Implementation 11. Throughput Optimization 12. Additional Features 13. Avalon-MM Testbench and Design Example 14. Avalon-MM Testbench and Design Example for Root Port 15. Hard IP Reconfiguration 16. Debugging A. PCI Express Protocol Stack B. Transaction Layer Packet (TLP) Header Formats C. Lane Initialization and Reversal D. Arria® 10 or Cyclone® 10 GX Avalon® -MM Interface for PCIe* Solutions User Guide Archive E. Document Revision History
1. Datasheet x
1.1. Arria® 10 or Cyclone® 10 GX Avalon-MM Interface for PCIe Datasheet 1.2. Features 1.3. Release Information 1.4. Device Family Support 1.5. Configurations 1.6. Design Examples 1.7. IP Core Verification 1.8. Resource Utilization 1.9. Recommended Speed Grades 1.10. Creating a Design for PCI Express
1.7. IP Core Verification x
1.7.1. Compatibility Testing Environment
2. Quick Start Guide x
2.1. Directory Structure 2.2. Design Components for the Avalon® -MM Endpoint 2.3. Generating the Design 2.4. Simulating the Design 2.5. Compiling and Testing the Design in Hardware
3. Parameter Settings x
3.1. Parameters 3.2. Avalon-MM Settings 3.3. Base Address Register (BAR) Settings 3.4. Device Identification Registers 3.5. PCI Express and PCI Capabilities Parameters 3.6. Configuration, Debug, and Extension Options 3.7. Vendor Specific Extended Capability (VSEC) 3.8. PHY Characteristics 3.9. Example Designs
3.5. PCI Express and PCI Capabilities Parameters x
3.5.1. Device Capabilities 3.5.2. Error Reporting 3.5.3. Link Capabilities 3.5.4. MSI and MSI-X Capabilities 3.5.5. Slot Capabilities 3.5.6. Power Management
4. Physical Layout x
4.1. Hard IP Block Placement In Cyclone® 10 GX Devices 4.2. Hard IP Block Placement In Arria® 10 Devices 4.3. Channel and Pin Placement for the Gen1, Gen2, and Gen3 Data Rates 4.4. Channel Placement and fPLL and ATX PLL Usage for the Gen3 Data Rate 4.5. PCI Express Gen3 Bank Usage Restrictions
5. 64- or 128-Bit Avalon-MM Interface to the Endpoint Application Layer x
5.1. 32-Bit Non-Bursting Avalon-MM Control Register Access (CRA) Slave Signals 5.2. Bursting and Non-Bursting Avalon® -MM Module Signals 5.3. 64- or 128-Bit Bursting TX Avalon-MM Slave Signals 5.4. Clock Signals 5.5. Reset, Status, and Link Training Signals 5.6. Interrupts for Endpoints when Multiple MSI/MSI-X Support Is Enabled 5.7. Hard IP Status Signals 5.8. Physical Layer Interface Signals
5.7. Hard IP Status Signals x
5.7.1. Hard IP Reconfiguration Interface
5.8. Physical Layer Interface Signals x
5.8.1. Serial Data Signals 5.8.2. PIPE Interface Signals 5.8.3. Arria® 10 Development Kit Conduit Interface 5.8.4. Test Signals
6. Registers x
6.1. Correspondence between Configuration Space Registers and the PCIe Specification 6.2. Type 0 Configuration Space Registers 6.3. Type 1 Configuration Space Registers 6.4. PCI Express Capability Structures 6.5. Intel-Defined VSEC Registers 6.6. CvP Registers 6.7. 64- or 128-Bit Avalon-MM Bridge Register Descriptions 6.8. Programming Model for Avalon-MM Root Port 6.9. Uncorrectable Internal Error Mask Register 6.10. Uncorrectable Internal Error Status Register 6.11. Correctable Internal Error Mask Register 6.12. Correctable Internal Error Status Register
6.7. 64- or 128-Bit Avalon-MM Bridge Register Descriptions x
6.7.1. Avalon-MM to PCI Express Interrupt Registers
6.7.1. Avalon-MM to PCI Express Interrupt Registers x
6.7.1.1. Avalon-MM to PCI Express Interrupt Status Registers 6.7.1.2. Avalon-MM to PCI Express Interrupt Enable Registers 6.7.1.3. PCI Express Mailbox Registers 6.7.1.4. Avalon-MM-to-PCI Express Address Translation Table 6.7.1.5. PCI Express to Avalon-MM Interrupt Status and Enable Registers for Endpoints 6.7.1.6. Avalon-MM Mailbox Registers 6.7.1.7. Control Register Access (CRA) Avalon-MM Slave Port
6.8. Programming Model for Avalon-MM Root Port x
6.8.1. Sending a Write TLP 6.8.2. Sending a Read TLP or Receiving a Non-Posted Completion TLP 6.8.3. Examples of Reading and Writing BAR0 Using the CRA Interface 6.8.4. PCI Express to Avalon-MM Interrupt Status and Enable Registers for Root Ports 6.8.5. Root Port TLP Data Registers
7. Reset and Clocks x
7.1. Reset Sequence for Hard IP for PCI Express IP Core and Application Layer 7.2. Clocks
7.2. Clocks x
7.2.1. Clock Domains 7.2.2. Clock Summary
7.2.1. Clock Domains x
7.2.1.1. coreclkout_hip 7.2.1.2. pld_clk
8. Interrupts for Endpoints x
8.1. Enabling MSI or Legacy Interrupts 8.2. Generation of Avalon-MM Interrupts 8.3. Interrupts for Endpoints Using the Avalon-MM Interface with Multiple MSI/MSI-X Support
9. Error Handling x
9.1. Physical Layer Errors 9.2. Data Link Layer Errors 9.3. Transaction Layer Errors 9.4. Error Reporting and Data Poisoning 9.5. Uncorrectable and Correctable Error Status Bits
10. Design Implementation x
10.1. Making Pin Assignments to Assign I/O Standard to Serial Data Pins 10.2. Recommended Reset Sequence to Avoid Link Training Issues 10.3. SDC Timing Constraints
11. Throughput Optimization x
11.1. Throughput of Posted Writes 11.2. Throughput of Non-Posted Reads
12. Additional Features x
12.1. Configuration over Protocol (CvP) 12.2. Autonomous Mode 12.3. ECRC
12.2. Autonomous Mode x
12.2.1. Enabling Autonomous Mode 12.2.2. Enabling CvP Initialization
12.3. ECRC x
12.3.1. ECRC on the RX Path 12.3.2. ECRC on the TX Path
13. Avalon-MM Testbench and Design Example x
13.1. Avalon-MM Endpoint Testbench 13.2. Endpoint Design Example 13.3. Avalon-MM Test Driver Module 13.4. Root Port BFM 13.5. BFM Procedures and Functions 13.6. Setting Up Simulation
13.2. Endpoint Design Example x
13.2.1. BAR/Address Map 13.2.2. BAR Setup
13.4. Root Port BFM x
13.4.1. Root Port BFM Overview 13.4.2. Issuing Read and Write Transactions to the Application Layer 13.4.3. Configuration of Root Port and Endpoint 13.4.4. Configuration Space Bus and Device Numbering 13.4.5. BFM Memory Map
13.5. BFM Procedures and Functions x
13.5.1. ebfm_barwr Procedure 13.5.2. ebfm_barwr_imm Procedure 13.5.3. ebfm_barrd_wait Procedure 13.5.4. ebfm_barrd_nowt Procedure 13.5.5. ebfm_cfgwr_imm_wait Procedure 13.5.6. ebfm_cfgwr_imm_nowt Procedure 13.5.7. ebfm_cfgrd_wait Procedure 13.5.8. ebfm_cfgrd_nowt Procedure 13.5.9. BFM Configuration Procedures 13.5.10. BFM Shared Memory Access Procedures 13.5.11. BFM Log and Message Procedures 13.5.12. Verilog HDL Formatting Functions
13.5.9. BFM Configuration Procedures x
13.5.9.1. ebfm_cfg_rp_ep Procedure 13.5.9.2. ebfm_cfg_decode_bar Procedure
13.5.10. BFM Shared Memory Access Procedures x
13.5.10.1. Shared Memory Constants 13.5.10.2. shmem_write Task 13.5.10.3. shmem_read Function 13.5.10.4. shmem_display Verilog HDL Function 13.5.10.5. shmem_fill Procedure 13.5.10.6. shmem_chk_ok Function
13.5.11. BFM Log and Message Procedures x
13.5.11.1. ebfm_display Verilog HDL Function 13.5.11.2. ebfm_log_stop_sim Verilog HDL Function 13.5.11.3. ebfm_log_set_suppressed_msg_mask Task 13.5.11.4. ebfm_log_set_stop_on_msg_mask Verilog HDL Task 13.5.11.5. ebfm_log_open Verilog HDL Function 13.5.11.6. ebfm_log_close Verilog HDL Function
13.5.12. Verilog HDL Formatting Functions x
13.5.12.1. himage1 13.5.12.2. himage2 13.5.12.3. himage4 13.5.12.4. himage8 13.5.12.5. himage16 13.5.12.6. dimage1 13.5.12.7. dimage2 13.5.12.8. dimage3 13.5.12.9. dimage4 13.5.12.10. dimage5 13.5.12.11. dimage6 13.5.12.12. dimage7
13.6. Setting Up Simulation x
13.6.1. Using the PIPE Interface for Gen1 and Gen2 Variants 13.6.2. Viewing the Important PIPE Interface Signals 13.6.3. Disabling the Scrambler for Gen1 and Gen2 Simulations 13.6.4. Disabling 8B/10B Encoding and Decoding for Gen1 and Gen2 Simulations
14. Avalon-MM Testbench and Design Example for Root Port x
14.1. Overview of the Design Example 14.2. Overview of the Simulation Testbench
14.1. Overview of the Design Example x
14.1.1. Example Design Generation 14.1.2. Directory Structure for the Generated Design Example
14.2. Overview of the Simulation Testbench x
14.2.1. Simulating the Design Example
15. Hard IP Reconfiguration x
15.1. Reconfigurable Read-Only Registers in the Hard IP for PCI Express
16. Debugging x
16.1. Simulation Fails To Progress Beyond Polling.Active State 16.2. Hardware Bring-Up Issues 16.3. Link Training 16.4. Creating a Signal Tap Debug File to Match Your Design Hierarchy 16.5. Use Third-Party PCIe Analyzer 16.6. BIOS Enumeration Issues
A. PCI Express Protocol Stack x
A.1. Top-Level Interfaces A.2. Data Link Layer A.3. Physical Layer A.4. 32-Bit PCI Express Avalon-MM Bridge A.5. Completer Only Single Dword Endpoint
A.1. Top-Level Interfaces x
A.1.1. Avalon-MM Interface A.1.2. Clocks and Reset A.1.3. Interrupts A.1.4. PIPE
A.4. 32-Bit PCI Express Avalon-MM Bridge x
A.4.1. Avalon‑MM Bridge TLPs A.4.2. Avalon-MM-to-PCI Express Write Requests A.4.3. Avalon-MM-to-PCI Express Upstream Read Requests A.4.4. PCI Express-to-Avalon-MM Read Completions A.4.5. PCI Express-to-Avalon-MM Downstream Write Requests A.4.6. PCI Express-to-Avalon-MM Downstream Read Requests A.4.7. Avalon-MM-to-PCI Express Read Completions A.4.8. PCI Express-to-Avalon-MM Address Translation for 32-Bit Bridge A.4.9. Minimizing BAR Sizes and the PCIe Address Space A.4.10. Avalon® -MM-to-PCI Express Address Translation Algorithm for 32-Bit Addressing
A.5. Completer Only Single Dword Endpoint x
A.5.1. RX Block A.5.2. Avalon-MM RX Master Block A.5.3. TX Block A.5.4. Interrupt Handler Block A.5.5. Preliminary Support for Root Port
B. Transaction Layer Packet (TLP) Header Formats x
B.1. TLP Packet Formats without Data Payload B.2. TLP Packet Formats with Data Payload
E. Document Revision History x
E.1. Document Revision History for the Arria® 10 and Cyclone® 10 GX Avalon® Memory Mapped (Avalon-MM) Interface for PCIe* Solutions User Guide
1. Datasheet
2. Quick Start Guide
3. Parameter Settings
4. Physical Layout
5. 64- or 128-Bit Avalon-MM Interface to the Endpoint Application Layer
6. Registers
7. Reset and Clocks
8. Interrupts for Endpoints
9. Error Handling
10. Design Implementation
11. Throughput Optimization
12. Additional Features
13. Avalon-MM Testbench and Design Example
14. Avalon-MM Testbench and Design Example for Root Port
15. Hard IP Reconfiguration
16. Debugging
A. PCI Express Protocol Stack
B. Transaction Layer Packet (TLP) Header Formats
C. Lane Initialization and Reversal
D. Arria® 10 or Cyclone® 10 GX Avalon® -MM Interface for PCIe* Solutions User Guide Archive
E. Document Revision History

E.1. Document Revision History for the Arria® 10 and Cyclone® 10 GX Avalon® Memory Mapped (Avalon-MM) Interface for PCIe* Solutions User Guide

Date

Version

Changes Made

2024.09.10 18.0 Added Notes with some reset recommendations to the Reset and Clocks section.
2024.04.13 18.0
  • Changed the signal name from altpcietb_bfm_driver_avmm.v to altpcietb_bfm_driver_downstream.v in section Avalon-MM Test Driver Module.
  • Made some editorial changes in section Avalon-MM Endpoint Testbench.
2023.11.29 18.0 Removed the configurations Gen3x8 - 256 bits, and Gen3x4 - 256 bits, from the table in the Recommended Speed Grades section as they are no longer supported.
2021.06.03 18.0 Mentioned in the Features section that this IP supports the Separate Reference Clock No Spread Spectrum (SRNS) architecture and not the Separate Reference Clock with Independent Spread Spectrum (SRIS) architecture.
2021.04.20 18.0 Updated the file where the parameter serial_sim_hwtcl needs to be set to 0 for PIPE simulations from altpcie_<dev>_tbed_hwtcl.v to DUT_pcie_tb_ip.v.
2021.04.06 18.0 Added the Hard IP Reconfiguration chapter containing descriptions of the registers that you can update using the Hard IP Reconfiguration interface.
2019.12.20 18.0 Changed the name of the 1A state of the ltssmstate signals to Recovery.Speed to follow the PCIe Specifications.
2019.10.09 18.0 Added State 1F (Recovery.Equalization, Done) for ltssmstate[4:0].
2019.09.30 18.0 Added more details about byte enable support in the Arria® 10 Root Port design example (in the Preliminary Support for Root Port section in the Appendix).
2019.05.23 18.0 Added the note clarifying that the 24-bit Class Code register is divided into three 8-bit fields: Base Class Code, Sub-Class Code and Programming Interface.
2018.08.13 18.0 Added the step to invoke Vsim to the instructions for running ModelSim simulations.
2018.08.03 18.0 Made the following changes to the user guide:
  • Removed a reference to the internal descriptor controller since that is an Avalon® -MM DMA feature and is covered in that User Guide.
  • Added text descriptions for the interfaces shown in Figure 27.
  • Updated signal names in Figure 27 to change rxm_bar0_* signals to rxm_bar<n>_* signals, where n is the BAR number and can range from 0 to 5.
  • Updated Tables 26 and 27 to change rxm_bar0_* signals to rxm_bar<n>_* signals.
  • Changed the title of Figure 30 to "Simultaneous RXM Read and RXM Write".
2018.05.07 18.0 Made the following changes to the user guide:
  • Changed Cyclone® 10 name to Cyclone® 10 GX.
  • Added CRA Read and Write timing diagrams.
  • Added missing link speeds/widths combinations to the Recommended Speed Grades table.
  • Removed any mention of static example designs in the Design Examples section.
  • Moved the topic on creating the .stp file from the Design Implementation chapter to the Debugging chapter.
  • Changed the title of the Optional Features chapter to Additional Features .
2017.10.06 17.1 Made the following changes to the user guide.
  • Added support for Cyclone® 10 GX devices.
  • Added Enable RX-polarity inversion soft logic parameter.
  • Corrected Feature Comparison for all Hard IP for PCI Express IP Core table: The Avalon-MM DMA interface does not automatically handle out-of-order completion s.
  • Rebranded as Intel.
2017.05.26 17.0 Made the following changes to the user guide:
  • Added note that starting with the Quartus® Prime Software, version 17.0, the QSF assignments in the following answer What assignments do I need for a PCIe Gen1, Gen2 or Gen3 design that targets an Arria® 10 ES2, ES3 or production device? are already included in the design.
2017.05.08 17.0

Made the following changes the IP core:

  • Added option soft DFE Controller IP on the PHY tab of the parameter editor to improve BER margin. The default for this option is off because it is typically not required. Short reflective links may benefit from this soft DFE controller IP. This parameter is available only for Gen3 configurations.

Made the following changes to the user guide:

  • Updated PCI Express Gen3 Bank Usage Restrictions status. These restrictions affect all Arria 10 ES and production devices.
  • Corrected Feature Comparison for all Hard IP for PCI Express IP Cores table. Out-of-order Completions are not supported transparently for the Avalon-MM with DMA interface.
  • Added Gen3 x8 Root Port to the Recommended Speed Grades for All Avalon-MM Widths and Frequencies table.
  • Corrected default values for the Uncorrectable Internal Error Mask Register and Correctable Internal Error Mask Register registers.
  • Corrected minor errors and typos.
2017.03.15 17.0
  • Removed Gen3x8 256-bit interface from Recommended Speed Grades table. This configuration is not supported for the Avalon-MM interface.
  • Added statement that Arria® 10 devices do not support the Create timing and resource estimates for third-party EDA synthesis tools option on the Generate > Generate HDL menu.
  • Rebranded as Intel.
2016.10.31 16.1

Made the following changes to the IP core:

  • Changed timing models support to final for most Arria® 10 device packages. Exceptions include some military and automotive speed grades with extended temperature ranges.
  • Added parameter to select the requested preset for Phase2 and Phase3 far-end TX equalization.

Made the following changes to the user guide:

  • Corrected the number of tags supported in the Feature Comparison for all Hard IP for PCI Express IP Cores table.
  • Removed recommendations about connecting pin_perst. These recommendations do not apply to Arria® 10 devices.
  • Added PCIe bifurcation to the Feature Comparison for all Hard IP for PCI Express IP Cores table. PCI bifurcation is not supported.
  • Changed the recommended value of test_in[31:0] from 0xa8 to 0x188.
  • Removed Configuration Space Register Access Timing timing diagram. These signals are not available at the top-level for the Avalon-MM interface.
  • Added instructions for turning on autonomous mode in the Quartus Prime software.
  • Added -3 to recommended speed grades for the 125 MHz interface.
2016.05.20 16.0

Added preliminary support for a Gen3 x8 Root Port using a 256-bit interface to the Application Layer.

Added support for Intel FPGA IP Evaluation Mode in the Quartus® Prime Pro Edition software.

Added automatic generation of basic Signal Tap Logic Analyzer files to facilitate debugging.

The PIO Design Examples included in the Quick Start Guide now support 64- and 128-bit interfaces to the Application Layer. (The 15.1 release supported only a 256-bit interface to the Application Layer interface.)

Updated figures in Physical Layout of Hard IP in Arria® 10 Devices to include more detail about transceiver banks and channel restrictions.

Revised description of TxsByteEnable_i[<w>-1:0] signal. This signal qualifies both read and write data.

Added Gen3 x2 128-bit interface with 125 MHz clock to the coreclkout_hip Application Layer Clock Frequency for All Combinations of Link Width, Data Rate and Application Layer Interface Widths table.

Clarified optimal read request size for typical systems that include the Avalon-MM TX slave interface.

In the Getting Started with the Hard IP for PCI Express with the Avalon-MM Interface chapter, changed the instructions to use specify the 10AX115S2F45I1SG device which is used on the Arria® 10 GX FPGA Development Kit - Production (not ES2) Edition.

Added Vendor Specific Extended Capability (VSEC) Revision and User Device or Board Type ID register from the Vendor Specific Extended Capability to the VSEC tab of the component GUI.

Added statement that the testbench can only simulate a single Endpoint or Root Port at a time.

Enhanced statements covering the deficiencies of the Altera-provided testbench.

Updated signal names to match those shown in the figure 64- or 128-Bit Avalon-MM Interface to the Application Layer.

Added transceiver bank usage placement restrictions for Gen3 ES3 devices.

Removed support for -3 speed grade devices.

Corrected minor errors and typos.
2015.11.02 15.1

Added new Generate Design Example option that automatically generates both simulation and hardware design examples with the parameters you specify. You can download the hardware design example directly to the Arria® 10 GX FPGA Development Kit.

Added preliminary support for Gen3 x4, Gen3 x8, and Gen2 x8 Root Port using a 256-bit Avalon-MM interface to the Application Layer.

Improved component GUI that simplifies parameterization. Among the changes is a new single parameter, HIP mode that combines all supported data rates, interface widths and frequencies as a single parameter.

Added support for Completion buffer overflow monitoring.

Improved the definition of npor.

Removed Legacy Endpoint option for Port Type parameter.

Clarified Application Layer requirements for multiple and single MSI and MSI-X support.

Corrected width of AVL_IRQ. It is 16 bits.

Added clarification for the use of byte enables with the 128-bit Avalon-MM bridge. Supported patterns for byte enables must be at the dword granularity.

Clarified Avalon-MM addressing for various data widths.

Renamed the data rate sim_pipe_rate to rate to match renaming for Arria® 10 devices.Made the following changes:

Removed support for the RP_RXCPL_STATUS field of the Root Port request register at 0x2010.

Added signal descriptions for optional hard IP status bus.

Fixed minor errors and typos.

2015.06.05 15.0 Added note in iPhysical Layout of Hard IP in Arria 10 Devices to explain Arria® 10 design constraint that requires that if the lower HIP on one side of the device is configured with a Gen3 x4 or Gen3 x8 IP core, and the upper HIP on the same side of the device is also configured with a Gen3 IP core, then the upper HIP must be configured with a x4 or x8 IP core.
2015.05.14 15.0 Made the following changes to the user guide:
  • Added Enable Hard IP Status Bus when using the AVMM interface parameter in Interface System Settings. This parameter is available in the IP core v15.0 and later.
2015.05.04 15.0 Made the following changes to the user guide:
  • Enhanced the descriptions in iAvalon-MM-to-PCI Express Address Translation Table.
  • Added Enable Altera Debug Master Endpoint (ADME) parameter to support optional Native PHY register programming with the Altera System Console.
  • Added support to send message TLPs with data payload of any length from a Root Port. Refer to Programming Model for Avalon-MM Root Port and to the new supported TLP entry for Avalon-MM variations in the Feature Comparison for all Hard IP for PCI Express IP Cores table in Features.
  • Added information about the new custom design examples, in the Design Examples section.
  • Added column for Avalon-ST Interface with SR-IOV variations in Feature Comparison for all Hard IP for PCI Express IP Cores table in the Features section.
  • Enhanced descriptions of channel placement, added fPLL placement for Gen1 and Gen2 data rates, and added master CGB location, in Physical Layout of Hard IP in Arria 10 Devices.
  • Updated DUT module name in testbench and design example figures.
  • Removed list of static design examples from Design Examples. You can derive the list from the installation directory where design examples are available.
  • Removed Migration and TLP Format appendices, and added new Frequently Asked Questions appendix.
  • Reorganized sections in Debugging and Setting Up Simulation. Removed Reducing Counter Values for Serial Simulations section, which is no longer relevant. Default counter values are automatically set for simulation.
  • Updated information in SDC Timing Constraints.
  • Fixed minor errors and typos.
2014.12.15 14.1 Made the following changes:
  • Revised Root Port programming model description, Receiving a Completion TLP, to cover read and non-posted completions.
  • Added Avalon-MM Testbench and Design Example chapter.
  • Added statement that the bottom left hard IP block includes the CvP functionality for flip chip packages. For other package types, the CvP functionality is in the bottom right block.
  • Corrected bit definitions for CvP Status register.
  • Updated definition of CVP_NUMCLKS in the CvP Mode Control register.
  • Added definitions for test_in[2], test_in[6], and test_in[7].
  • Revised discussion of SDC files to include in Quartus II project.
2014.08.18 14.0 Arria® 10

Made the following changes to the Arria® 10 Avalon-MM Hard IP for PCI Express

  • Optionally changed the cra_address to 14 bits from 12.
  • Added simulation log file, altpcie_monitor_a10_dlhip_tlp_file_log.log, that is automatically generated in your simulation directory. To simulate in the Quartus II 14.0 software release, you must regenerate your IP core to create the supporting monitor file the generates altpcie_monitor_a10_dlhip_tlp_file_log.log. Refer to Understanding Simulation Dump File Generation for details.
  • Added support for 64-bit addressing, making address translation unnecessary.
  • Removed Channel Placement for PCIe in Arria 10 Devices. Please contact your Altera sales representative for PLL and channel usage.
  • Added simulation support for Phase 2 and Phase 3 equalization when requested by third-party BFM.
  • Added restrictions on the legal patterns of enabled and disabled bytes for txs_byteenable[<w>-1:0].
  • Changed the PIPE interface to 32 bits for all data rates. This change requires you to recompile your 13.1 variant in 14.0.
Made the following changes to the user guide:
  • Changed device part number for Getting Started chapter to 10AX115R2F40I2LG.
  • Corrected frequency range for hip_reconfig_clk. It should be 100-125 MHz.
  • Clarified the behavior of the txs_waitrequest signal.
  • Added statement that the bottom left hard IP block includes the CvP functionality for flip chip packages. For other package types, the CvP functionality is in the bottom right block.
  • Simplified the Getting Started chapter. It copies the example from the install directory and does not include step-by-step instructions to recreate the design.
  • Removed 125 MHz clock as optional refclk frequency in Arria® 10 devices. Arria® 10 devices support an 100 MHz reference clock as specified by the PCI Express Base Specification, Rev 3.0.
  • Added definitions for test_in[2], test_in[6] and test_in[7].
  • Clarified that the Avalon-MM Bridge does not generate out-of-order Avalon-MM-to-PCI Express Read Completions even to different BARs.
  • Added sections on making analog QSF and pin assignments.
  • Enhanced the definition of Device ID and Sub-system Vendor ID to say that these registers are only valid in the Type 0 (Endpoint) Configuration Space.
  • Updated Power Supply Voltage Requirements table.
  • Removed all references to the Avalon-MM interrupt vector register. This register is not used.
  • Corrected values for Maximum payload size parameter. The sizes available are 128 or 256 bytes.
  • Removed txdatavalid0 signal from the PIPE interface. This signal is not available.
  • Updated Power Supply Voltage Requirements table.
  • Updated Physical Placement of the Arria 10 Hard IP for PCIe IP and Channels to show GT devices instead of GX devices.
  • Corrected bit definitions for CvP Status register.
  • Updated definition of CVP_NUMCLKS in the CvP Mode Control register.
  • Removed discussion of pclk. This clock is not customer accessible in Arria® 10 devices.
  • Removed PLL from channel placement figures.
  • Added fast passive parallel (FPP) to supported configuration schemes in CvP in Arria® 10 Devices figure.
  • Corrected Reset Controller in Arria® 10 Devices figure in Reset and Clocks chapter.
  • Corrected bit definitions for CvP Status register.
2013.12.02 13.1 Arria® 10 Initial release.
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