Arria® 10 and Cyclone® 10 GX Avalon® Memory-Mapped (Avalon-MM) Interface for PCI Express* User Guide

Download PDF
ID 683724
Date 9/10/2024
Public
Document Table of Contents
Document Table of Contents x
1. Datasheet 2. Quick Start Guide 3. Parameter Settings 4. Physical Layout 5. 64- or 128-Bit Avalon-MM Interface to the Endpoint Application Layer 6. Registers 7. Reset and Clocks 8. Interrupts for Endpoints 9. Error Handling 10. Design Implementation 11. Throughput Optimization 12. Additional Features 13. Avalon-MM Testbench and Design Example 14. Avalon-MM Testbench and Design Example for Root Port 15. Hard IP Reconfiguration 16. Debugging A. PCI Express Protocol Stack B. Transaction Layer Packet (TLP) Header Formats C. Lane Initialization and Reversal D. Arria® 10 or Cyclone® 10 GX Avalon® -MM Interface for PCIe* Solutions User Guide Archive E. Document Revision History
1. Datasheet x
1.1. Arria® 10 or Cyclone® 10 GX Avalon-MM Interface for PCIe Datasheet 1.2. Features 1.3. Release Information 1.4. Device Family Support 1.5. Configurations 1.6. Design Examples 1.7. IP Core Verification 1.8. Resource Utilization 1.9. Recommended Speed Grades 1.10. Creating a Design for PCI Express
1.7. IP Core Verification x
1.7.1. Compatibility Testing Environment
2. Quick Start Guide x
2.1. Directory Structure 2.2. Design Components for the Avalon® -MM Endpoint 2.3. Generating the Design 2.4. Simulating the Design 2.5. Compiling and Testing the Design in Hardware
3. Parameter Settings x
3.1. Parameters 3.2. Avalon-MM Settings 3.3. Base Address Register (BAR) Settings 3.4. Device Identification Registers 3.5. PCI Express and PCI Capabilities Parameters 3.6. Configuration, Debug, and Extension Options 3.7. Vendor Specific Extended Capability (VSEC) 3.8. PHY Characteristics 3.9. Example Designs
3.5. PCI Express and PCI Capabilities Parameters x
3.5.1. Device Capabilities 3.5.2. Error Reporting 3.5.3. Link Capabilities 3.5.4. MSI and MSI-X Capabilities 3.5.5. Slot Capabilities 3.5.6. Power Management
4. Physical Layout x
4.1. Hard IP Block Placement In Cyclone® 10 GX Devices 4.2. Hard IP Block Placement In Arria® 10 Devices 4.3. Channel and Pin Placement for the Gen1, Gen2, and Gen3 Data Rates 4.4. Channel Placement and fPLL and ATX PLL Usage for the Gen3 Data Rate 4.5. PCI Express Gen3 Bank Usage Restrictions
5. 64- or 128-Bit Avalon-MM Interface to the Endpoint Application Layer x
5.1. 32-Bit Non-Bursting Avalon-MM Control Register Access (CRA) Slave Signals 5.2. Bursting and Non-Bursting Avalon® -MM Module Signals 5.3. 64- or 128-Bit Bursting TX Avalon-MM Slave Signals 5.4. Clock Signals 5.5. Reset, Status, and Link Training Signals 5.6. Interrupts for Endpoints when Multiple MSI/MSI-X Support Is Enabled 5.7. Hard IP Status Signals 5.8. Physical Layer Interface Signals
5.7. Hard IP Status Signals x
5.7.1. Hard IP Reconfiguration Interface
5.8. Physical Layer Interface Signals x
5.8.1. Serial Data Signals 5.8.2. PIPE Interface Signals 5.8.3. Arria® 10 Development Kit Conduit Interface 5.8.4. Test Signals
6. Registers x
6.1. Correspondence between Configuration Space Registers and the PCIe Specification 6.2. Type 0 Configuration Space Registers 6.3. Type 1 Configuration Space Registers 6.4. PCI Express Capability Structures 6.5. Intel-Defined VSEC Registers 6.6. CvP Registers 6.7. 64- or 128-Bit Avalon-MM Bridge Register Descriptions 6.8. Programming Model for Avalon-MM Root Port 6.9. Uncorrectable Internal Error Mask Register 6.10. Uncorrectable Internal Error Status Register 6.11. Correctable Internal Error Mask Register 6.12. Correctable Internal Error Status Register
6.7. 64- or 128-Bit Avalon-MM Bridge Register Descriptions x
6.7.1. Avalon-MM to PCI Express Interrupt Registers
6.7.1. Avalon-MM to PCI Express Interrupt Registers x
6.7.1.1. Avalon-MM to PCI Express Interrupt Status Registers 6.7.1.2. Avalon-MM to PCI Express Interrupt Enable Registers 6.7.1.3. PCI Express Mailbox Registers 6.7.1.4. Avalon-MM-to-PCI Express Address Translation Table 6.7.1.5. PCI Express to Avalon-MM Interrupt Status and Enable Registers for Endpoints 6.7.1.6. Avalon-MM Mailbox Registers 6.7.1.7. Control Register Access (CRA) Avalon-MM Slave Port
6.8. Programming Model for Avalon-MM Root Port x
6.8.1. Sending a Write TLP 6.8.2. Sending a Read TLP or Receiving a Non-Posted Completion TLP 6.8.3. Examples of Reading and Writing BAR0 Using the CRA Interface 6.8.4. PCI Express to Avalon-MM Interrupt Status and Enable Registers for Root Ports 6.8.5. Root Port TLP Data Registers
7. Reset and Clocks x
7.1. Reset Sequence for Hard IP for PCI Express IP Core and Application Layer 7.2. Clocks
7.2. Clocks x
7.2.1. Clock Domains 7.2.2. Clock Summary
7.2.1. Clock Domains x
7.2.1.1. coreclkout_hip 7.2.1.2. pld_clk
8. Interrupts for Endpoints x
8.1. Enabling MSI or Legacy Interrupts 8.2. Generation of Avalon-MM Interrupts 8.3. Interrupts for Endpoints Using the Avalon-MM Interface with Multiple MSI/MSI-X Support
9. Error Handling x
9.1. Physical Layer Errors 9.2. Data Link Layer Errors 9.3. Transaction Layer Errors 9.4. Error Reporting and Data Poisoning 9.5. Uncorrectable and Correctable Error Status Bits
10. Design Implementation x
10.1. Making Pin Assignments to Assign I/O Standard to Serial Data Pins 10.2. Recommended Reset Sequence to Avoid Link Training Issues 10.3. SDC Timing Constraints
11. Throughput Optimization x
11.1. Throughput of Posted Writes 11.2. Throughput of Non-Posted Reads
12. Additional Features x
12.1. Configuration over Protocol (CvP) 12.2. Autonomous Mode 12.3. ECRC
12.2. Autonomous Mode x
12.2.1. Enabling Autonomous Mode 12.2.2. Enabling CvP Initialization
12.3. ECRC x
12.3.1. ECRC on the RX Path 12.3.2. ECRC on the TX Path
13. Avalon-MM Testbench and Design Example x
13.1. Avalon-MM Endpoint Testbench 13.2. Endpoint Design Example 13.3. Avalon-MM Test Driver Module 13.4. Root Port BFM 13.5. BFM Procedures and Functions 13.6. Setting Up Simulation
13.2. Endpoint Design Example x
13.2.1. BAR/Address Map 13.2.2. BAR Setup
13.4. Root Port BFM x
13.4.1. Root Port BFM Overview 13.4.2. Issuing Read and Write Transactions to the Application Layer 13.4.3. Configuration of Root Port and Endpoint 13.4.4. Configuration Space Bus and Device Numbering 13.4.5. BFM Memory Map
13.5. BFM Procedures and Functions x
13.5.1. ebfm_barwr Procedure 13.5.2. ebfm_barwr_imm Procedure 13.5.3. ebfm_barrd_wait Procedure 13.5.4. ebfm_barrd_nowt Procedure 13.5.5. ebfm_cfgwr_imm_wait Procedure 13.5.6. ebfm_cfgwr_imm_nowt Procedure 13.5.7. ebfm_cfgrd_wait Procedure 13.5.8. ebfm_cfgrd_nowt Procedure 13.5.9. BFM Configuration Procedures 13.5.10. BFM Shared Memory Access Procedures 13.5.11. BFM Log and Message Procedures 13.5.12. Verilog HDL Formatting Functions
13.5.9. BFM Configuration Procedures x
13.5.9.1. ebfm_cfg_rp_ep Procedure 13.5.9.2. ebfm_cfg_decode_bar Procedure
13.5.10. BFM Shared Memory Access Procedures x
13.5.10.1. Shared Memory Constants 13.5.10.2. shmem_write Task 13.5.10.3. shmem_read Function 13.5.10.4. shmem_display Verilog HDL Function 13.5.10.5. shmem_fill Procedure 13.5.10.6. shmem_chk_ok Function
13.5.11. BFM Log and Message Procedures x
13.5.11.1. ebfm_display Verilog HDL Function 13.5.11.2. ebfm_log_stop_sim Verilog HDL Function 13.5.11.3. ebfm_log_set_suppressed_msg_mask Task 13.5.11.4. ebfm_log_set_stop_on_msg_mask Verilog HDL Task 13.5.11.5. ebfm_log_open Verilog HDL Function 13.5.11.6. ebfm_log_close Verilog HDL Function
13.5.12. Verilog HDL Formatting Functions x
13.5.12.1. himage1 13.5.12.2. himage2 13.5.12.3. himage4 13.5.12.4. himage8 13.5.12.5. himage16 13.5.12.6. dimage1 13.5.12.7. dimage2 13.5.12.8. dimage3 13.5.12.9. dimage4 13.5.12.10. dimage5 13.5.12.11. dimage6 13.5.12.12. dimage7
13.6. Setting Up Simulation x
13.6.1. Using the PIPE Interface for Gen1 and Gen2 Variants 13.6.2. Viewing the Important PIPE Interface Signals 13.6.3. Disabling the Scrambler for Gen1 and Gen2 Simulations 13.6.4. Disabling 8B/10B Encoding and Decoding for Gen1 and Gen2 Simulations
14. Avalon-MM Testbench and Design Example for Root Port x
14.1. Overview of the Design Example 14.2. Overview of the Simulation Testbench
14.1. Overview of the Design Example x
14.1.1. Example Design Generation 14.1.2. Directory Structure for the Generated Design Example
14.2. Overview of the Simulation Testbench x
14.2.1. Simulating the Design Example
15. Hard IP Reconfiguration x
15.1. Reconfigurable Read-Only Registers in the Hard IP for PCI Express
16. Debugging x
16.1. Simulation Fails To Progress Beyond Polling.Active State 16.2. Hardware Bring-Up Issues 16.3. Link Training 16.4. Creating a Signal Tap Debug File to Match Your Design Hierarchy 16.5. Use Third-Party PCIe Analyzer 16.6. BIOS Enumeration Issues
A. PCI Express Protocol Stack x
A.1. Top-Level Interfaces A.2. Data Link Layer A.3. Physical Layer A.4. 32-Bit PCI Express Avalon-MM Bridge A.5. Completer Only Single Dword Endpoint
A.1. Top-Level Interfaces x
A.1.1. Avalon-MM Interface A.1.2. Clocks and Reset A.1.3. Interrupts A.1.4. PIPE
A.4. 32-Bit PCI Express Avalon-MM Bridge x
A.4.1. Avalon‑MM Bridge TLPs A.4.2. Avalon-MM-to-PCI Express Write Requests A.4.3. Avalon-MM-to-PCI Express Upstream Read Requests A.4.4. PCI Express-to-Avalon-MM Read Completions A.4.5. PCI Express-to-Avalon-MM Downstream Write Requests A.4.6. PCI Express-to-Avalon-MM Downstream Read Requests A.4.7. Avalon-MM-to-PCI Express Read Completions A.4.8. PCI Express-to-Avalon-MM Address Translation for 32-Bit Bridge A.4.9. Minimizing BAR Sizes and the PCIe Address Space A.4.10. Avalon® -MM-to-PCI Express Address Translation Algorithm for 32-Bit Addressing
A.5. Completer Only Single Dword Endpoint x
A.5.1. RX Block A.5.2. Avalon-MM RX Master Block A.5.3. TX Block A.5.4. Interrupt Handler Block A.5.5. Preliminary Support for Root Port
B. Transaction Layer Packet (TLP) Header Formats x
B.1. TLP Packet Formats without Data Payload B.2. TLP Packet Formats with Data Payload
E. Document Revision History x
E.1. Document Revision History for the Arria® 10 and Cyclone® 10 GX Avalon® Memory Mapped (Avalon-MM) Interface for PCIe* Solutions User Guide
1. Datasheet
2. Quick Start Guide
3. Parameter Settings
4. Physical Layout
5. 64- or 128-Bit Avalon-MM Interface to the Endpoint Application Layer
6. Registers
7. Reset and Clocks
8. Interrupts for Endpoints
9. Error Handling
10. Design Implementation
11. Throughput Optimization
12. Additional Features
13. Avalon-MM Testbench and Design Example
14. Avalon-MM Testbench and Design Example for Root Port
15. Hard IP Reconfiguration
16. Debugging
A. PCI Express Protocol Stack
B. Transaction Layer Packet (TLP) Header Formats
C. Lane Initialization and Reversal
D. Arria® 10 or Cyclone® 10 GX Avalon® -MM Interface for PCIe* Solutions User Guide Archive
E. Document Revision History

A.4.9. Minimizing BAR Sizes and the PCIe Address Space

For designs that include multiple BARs, you may need to modify the base address assignments auto‑assigned by Platform Designer in order to minimize the address space that the BARs consume. For example, consider a Platform Designer system with the following components:

  • Offchip_Data_Mem DDR3 (SDRAM Controller with UniPHY) controlling 256 MB of memory—Platform Designer auto‑assigned a base address of 0x00000000
  • Quick_Data_Mem (On-Chip Memory (RAM or ROM)) of 4 KB—Platform Designer auto‑assigned a base address of 0x10000000
  • Instruction_Mem (On-Chip Memory (RAM or ROM)) of 64 KB—Platform Designer auto‑assigned a base address of 0x10020000
  • PCIe (Avalon‑MM Arria® 10 or Cyclone® 10 GX Hard IP for PCI Express)
    • Cra (Avalon‑MM Slave)—auto assigned base address of 0x10004000
    • Rxm_BAR0 connects to Offchip_Data_Mem DD R3 avl
    • Rxm_BAR2 connects to Quick_Data_Mem s1
    • Rxm_BAR4 connects to PCIe. Cra Avalon MM Slave
  • Nios2 (Nios® II Processor)
    • data_master connects to PCIe Cra, Offchip_Data_Mem DDR3 avl, Quick_Data_Mem s1, Instruction_Mem s1, Nios2 jtag_debug_module
    • instruction_master connects to Instruction_Mem s1
Figure 73.  Platform Designer System for PCI Express with Poor Address Space UtilizationThe following figure uses a filter to hide the Conduit interfaces that are not relevant in this discussion.
Figure 74. Poor Address MapThe following figure illustrates the address map for this system.

The auto‑assigned base addresses result in the following three large BARs:

  • BAR0 is 28 bits. This is the optimal size because it addresses the Offchip_Data_Mem which requires 28 address bits.
  • BAR2 is 29 bits. BAR2 addresses the Quick_Data_Mem which is 4 KB. It should only require 12 address bits; however, it is consuming 512 MBytes of address space.
  • BAR4 is also 29 bits. BAR4 address PCIe Cra is 16 KB. It should only require 14 address bits; however, it is also consuming 512 MB of address space.

This design is consuming 1.25 GB of PCIe address space when only 276 MB are actually required. The solution is to edit the address map to place the base address of each BAR at 0x0000_0000. The following figure illustrates the optimized address map.

Figure 75. Optimized Address Map
Figure 76. Reduced Address Bits for BAR2 and BAR4The following figure shows the number of address bits required when the smaller memories accessed by BAR2 and BAR4 have a base address of 0x0000_0000.

For cases where the BAR Avalon-MM RX master port connects to more than one Avalon‑MM slave, assign the base addresses of the slaves sequentially and place the slaves in the smallest power‑of‑two‑sized address space possible. Doing so minimizes the system address space used by the BAR.

Level Two Title