Visible to Intel only — GUID: lbl1417474540624
Ixiasoft
Visible to Intel only — GUID: lbl1417474540624
Ixiasoft
1.2. Features
New features in the Quartus® Prime 18.0 software release:
- Added support for Cyclone® 10 GX devices for up to Gen2 x4 configurations.
- Added optional parameter to invert the RX polarity.
The Arria® 10 or Cyclone® 10 GX Hard IP for PCI Express with the Avalon-MM interface supports the following features:
- Complete protocol stack including the Transaction, Data Link, and Physical Layers implemented as hard IP.
- Support for ×1, ×2, ×4, and ×8 configurations with Gen1, Gen2, or Gen3 lane rates for Arria® 10 Root Ports and Endpoints.
- Support for ×1, ×2, and ×4 configurations with Gen1 or Gen2 lane rates for Cyclone® 10 GX Root Ports and Endpoints.
- Dedicated 16 KB receive buffer.
- Optional support for Configuration via Protocol (CvP) using the PCIe link allowing the I/O and core bitstreams to be stored separately.
- Support for 32- or 64-bit addressing for the Avalon-MM interface to the Application Layer.
- Platform Designer design example demonstrating parameterization, design modules, and connectivity.
- Extended credit allocation settings to better optimize the RX buffer space based on application type.
- Optional end-to-end cyclic redundancy code (ECRC) generation and checking and advanced error reporting (AER) for high reliability applications.
- Support for Separate Reference Clock No Spread Spectrum (SRNS) architecture. The Separate Reference Clock with Independent Spread Spectrum (SRIS) architecture is not supported.
- Easy to use:
- Flexible configuration.
- No license requirement.
- Design examples to get started.
Feature |
Avalon-ST Interface |
Avalon-MM Interface |
Avalon-MM DMA |
---|---|---|---|
IP Core License |
Free |
Free |
Free |
Native Endpoint |
Supported |
Supported |
Supported |
Root port |
Supported |
Supported |
Not supported |
Gen1 |
×1, ×2, ×4, ×8 |
×1, ×2, ×4, ×8 |
x8 |
Gen2 |
×1, ×2, ×4, ×8 |
×1, ×2, ×4, ×8 |
×4, ×8 |
Gen3 |
×1, ×2, ×4, ×8 |
×1, ×2, ×4, x8 1 |
×2, ×4, ×8 |
64-bit Application Layer interface |
Supported |
Supported |
Not supported |
128-bit Application Layer interface |
Supported |
Supported |
Supported |
256‑bit Application Layer interface |
Supported |
Supported |
Supported |
Maximum payload size |
128, 256, 512, 1024, 2048 bytes |
128, 256 bytes |
128, 256 bytes |
Number of tags supported for non-posted requests |
32, 64, 128, or 256 |
8 for the 64-bit interface 16 for the 128-bit interface and 256-bit interface |
16 or 256 |
Automatically handle out-of-order completions (transparent to the Application Layer) |
Not supported |
Not Supported |
Not Supported |
Automatically handle requests that cross 4 KB address boundary (transparent to the Application Layer) |
Not supported |
Supported |
Supported |
Polarity Inversion of PIPE interface signals |
Supported |
Supported |
Supported |
Number of MSI requests |
1, 2, 4, 8, 16, or 32 |
1, 2, 4, 8, 16, or 32 2 |
1, 2, 4, 8, 16, or 32 3 |
MSI-X |
Supported |
Supported |
Supported |
Legacy interrupts |
Supported |
Supported |
Supported |
Expansion ROM |
Supported |
Not supported |
Not supported |
PCIe bifurcation | Not supported | Not supported | Not supported |
TLP (Transmit Support) |
Avalon-ST Interface |
Avalon-MM Interface |
Avalon-MM DMA |
---|---|---|---|
Memory Read Request (Mrd) | EP/RP | EP/RP | EP (Read DMA Avalon-MM Master) |
Memory Read Lock Request (MRdLk) | EP/RP | Not supported | Not supported |
Memory Write Request (MWr) | EP/RP | EP/RP | EP (Write DMA Avalon-MM Master) TX Slave (optional) |
I/O Read Request (IORd) | EP/RP | EP/RP | Not supported |
I/O Write Request (IOWr) | EP/RP | EP/RP | Not supported |
Config Type 0 Read Request (CfgRd0) | RP | RP | Not supported |
Config Type 0 Write Request (CfgWr0) | RP | RP | Not supported |
Config Type 1 Read Request (CfgRd1) | RP | RP | Not supported |
Config Type 1 Write Request (CfgWr1) | RP | RP | Not supported |
Message Request (Msg) | EP/RP | Not supported | Not supported |
Message Request with Data (MsgD) | EP/RP | Not supported | Not supported |
Completion with Data (CplD) | EP/RP | EP/RP | EP (Read & Write DMA Avalon-MM Masters) |
Completion-Locked (CplLk) | EP/RP | Not supported | Not supported |
Completion Lock with Data (CplDLk) | EP/RP | Not supported | Not supported |
Fetch and Add AtomicOp Request (FetchAdd) | EP | Not supported | Not supported |
The Arria® 10 or Cyclone® 10 GX Avalon-MM Interface for PCIe Solutions User Guide explains how to use this IP core and not the PCI Express protocol. Although there is inevitable overlap between these two purposes, use this document only in conjunction with an understanding of the PCI Express Base Specification.