Virtual JTAG Intel® FPGA IP Core User Guide

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ID 683705
Date 8/12/2021
Public
Document Table of Contents
Document Table of Contents x
Virtual JTAG Intel® FPGA IP Core User Guide
Virtual JTAG Intel® FPGA IP Core User Guide x
Introduction System-Level Debugging Infrastructure Virtual JTAG Interface Description Run-Time Communication Instantiating the Virtual JTAG Intel® FPGA IP Core Simulation Support Compiling the Design SLD_NODE Discovery and Enumeration Capturing the Virtual IR Instruction Register AHDL Function Prototype VHDL Component Declaration VHDL LIBRARY-USE Declaration Design Example: TAP Controller State Machine Design Example: Modifying the DCFIFO Contents at Runtime Design Example: Offloading Hardwired Revision Information Document Revision History for the Virtual JTAG Intel® FPGA IP Core User Guide
Introduction x
Installing and Licensing Intel® FPGA IP Cores On-Chip Debugging Tool Suite Applications of the Virtual JTAG Intel® FPGA IP Core JTAG Protocol JTAG Circuitry Architecture
System-Level Debugging Infrastructure x
Transaction Model of the SLD Infrastructure SLD Hub Finite State Machine
Virtual JTAG Interface Description x
Input Ports Output Ports Parameters Design Flow of the Virtual JTAG Intel® FPGA IP Core Simulation Model Run-Time Communication Running a DR Shift Operation Through a Virtual JTAG Chain
Run-Time Communication x
Virtual IR/DR Shift Transaction without Returning Captured IR/DR Values Virtual IR/DR Shift Transaction that Captures Current VIR/VDR Values Reset Considerations when Using a Custom JTAG Controller
Instantiating the Virtual JTAG Intel® FPGA IP Core x
IP Catalog and Parameter Editor Specifying IP Core Parameters and Options Instantiating Directly in HDL
IP Catalog and Parameter Editor x
The Parameter Editor
Specifying IP Core Parameters and Options x
Files Generated for Intel® FPGA IP Cores (Legacy Parameter Editor)
Compiling the Design x
Third-Party Synthesis Support
SLD_NODE Discovery and Enumeration x
Issuing the HUB_INFO Instruction HUB IP Configuration Register SLD_NODE Info Register
Design Example: Modifying the DCFIFO Contents at Runtime x
Write Logic Read Logic Runtime Communication
Design Example: Offloading Hardwired Revision Information x
Configuring the JTAG User Code Setting
Virtual JTAG Intel® FPGA IP Core User Guide

Run-Time Communication

The Tcl API for the Virtual JTAG Intel® FPGA IP core consists of a set of commands for accessing the VIR and VDR of each virtual JTAG instance.

These commands contain the underlying drivers for accessing an Intel® programming cable and for issuing shift transactions to each VIR and VDR. The table below provides the Tcl commands in the quartus_stp executable that you can use with the Virtual JTAG Intel® FPGA IP core, and are intended for designs that use a custom controller to drive the JTAG chain.

Each instantiation of the Virtual JTAG Intel® FPGA IP core includes an instance index. All instances are sequentially numbered and are automatically provided by the Quartus® Prime software. The instance index starts at instance index 0. The VIR and VDR shift commands described in the table decode the instance index and provide an address to the SLD hub for each IP core instance. You can override the default index provided by the Quartus® Prime software during configuration of the IP core.

The table below provides the Tcl commands in the quartus_stp executable that you can use with the Virtual JTAG Intel® FPGA IP core, and are intended for designs that use a custom controller to drive the JTAG chain.

Table 7.  Virtual JTAG Intel® FPGA IP Core Tcl Commands  

Command

Arguments

Description

Device virtual ir shift

-instance_index <instance_index>

-ir_value <numeric_ir_value>

-no_captured_ir_value 1

-show_equivalent_device_ir_dr_shift 1

Perform an IR shift operation to the virtual JTAG instance specified by the instance_index. Note that ir_value takes a numerical argument.

Device virtual dr shift

-instance_index <instance_index>

-dr_value <dr_value>

-length <data_register_length>

-no_captured_dr_value 1

-show_equivalent_device_ir_dr_shift

-value_in_hex 1

Perform a DR shift operation to the virtual JTAG instance.

Get hardware names

NONE

Queries for all available programming cables.

Open device

-device_name <device_name>

-hardware_name <hardware_name>

Selects the active device on the JTAG chain.

Close device

NONE

Ends communication with the active JTAG device.

Device lock

-timeout <timeout>

Obtains exclusive communication to the JTAG chain.

Device unlock

NONE

Releases device_lock.

Device ir shift

-ir_value <ir_value>

-no_captured_ir_value

Performs a IR shift operation.

Device dr shift

-dr_value <dr_value>

-length <data register length>

-no_captured_dr_value

-value_in_hex

Performs a DR shift operation.

Central to Virtual JTAG Intel® FPGA IP core are the device_virtual_ir_shift and device_virtual_dr_shift commands. These commands perform the shift operation to each VIR/VDR and provide the address to the SLD hub for the active JTAG datapath.

Each device_virtual_ir_shift command issues a USER1 instruction to the JTAG Instruction Register followed by a DR shift containing the VIR value provided by the ir_value argument prepended by address bits to target the correct SLD node instance.

Note:

Use the -no_captured_ir_value argument if you do not care about shifting out the contents of the current VIR value. Enabling this argument increases the speed of the VIR shift transaction by eliminating a command cycle within the underlying transaction.

Similarly, each device_virtual_dr_shift command issues a USER0 instruction to the JTAG Instruction Register followed by a DR shift containing the VDR value provided by the dr_value argument. These commands return the underlying JTAG transactions with the show_equivalent_device_ir_dr_shift option set.

Note:

The device_virtual_ir_shift takes the ir_value argument as a numeric value. The device_virtual_dr_shift takes the dr_value argument by either a binary string or a hexadecimal string. Do not use numeric values for the device_virtual_dr_shift.

1 This argument is optional.
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