AN 954: Hierarchical Partial Reconfiguration Tutorial: for the Intel Agilex® 7 FPGA Development Board

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ID 683687
Date 1/16/2024
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Document Table of Contents
Document Table of Contents x
Answers to Top FAQs Hierarchical Partial Reconfiguration Tutorial for the Intel Agilex® 7 FPGA Development Board
Hierarchical Partial Reconfiguration Tutorial for the Intel Agilex® 7 FPGA Development Board x
Reference Design Overview Reference Design Requirements Reference Design Files Reference Design Walkthrough Document Revision History for AN 954: Hierarchical Partial Reconfiguration Tutorial for Intel Agilex® 7 FPGA Development Board
Reference Design Walkthrough x
Step 1: Getting Started Step 2: Creating a Child Level Submodule Step 3: Creating Design Partitions Step 4: Allocating Placement and Routing Region for PR Partitions Step 5: Defining Personas Step 6: Creating Revisions Step 7: Compiling the Base Revision Step 8: Preparing the PR Implementation Revisions for Parent PR Partition Step 9: Preparing the PR Implementation Revisions for Child PR Partitions Step 10: Programming the Board Modifying an Existing Persona Adding a New Persona to the Design
Step 6: Creating Revisions x
Setting the Base Revision Type Creating Implementation Revisions
Step 10: Programming the Board x
Programming the Child PR Region
Answers to Top FAQs
Hierarchical Partial Reconfiguration Tutorial for the Intel Agilex® 7 FPGA Development Board

Step 10: Programming the Board

This tutorial uses an Intel Agilex® 7 F-Series or M-Series FPGA development board on the bench, outside of the PCIe* slot in your host machine. Before you program the board, ensure that you have completed the following steps:

  1. Connect the power supply to the Intel Agilex® 7 F-Series or M-Series FPGA development board.
  2. Connect the Intel® FPGA Download Cable between your PC USB port and the Intel® FPGA Download Cable port on the development board.

To run the design on the Intel Agilex® 7 F-Series or M-Series FPGA development board:

  1. Open the Intel® Quartus® Prime software and click Tools > Programmer.
  2. In the Programmer, click Hardware Setup and select USB-Blaster.
  3. Click Auto Detect and select the appropriate device for your development kit.
  4. Click OK. The Intel® Quartus® Prime software detects and updates the Programmer with the three FPGA chips on the board.
  5. Select the Intel Agilex® 7 device, click Change File and load the blinking_led.sof file.
  6. Enable Program/Configure for blinking_led.sof file.
  7. Click Start and wait for the progress bar to reach 100%.
  8. Observe the LEDs on the board blinking at the same frequency as the original flat design.
  9. To program only the child PR region, right-click the blinking_led.sof file in the Programmer and click Add PR Programming File.
  10. Select the hpr_child_slow.pr_parent_partition.pr_partition.rbf file.
  11. Disable Program/Configure for blinking_led.sof file.
  12. Enable Program/Configure for hpr_child_slow.pr_parent_partition.pr_partition.rbf file and click Start. On the board, observe LED[0] and LED[1] continuing to blink. When the progress bar reaches 100%, LED[2] blinks at the same rate, and LED[3] blinks slower.
  13. To program both the parent and child PR region, right-click the .rbf file in the Programmer and click Change PR Programing File.
  14. Select the hpr_parent_slow_child_slow.pr_parent_partition.rbf file.
  15. Click Start. On the board, observe that LED[0] and LED[1] continuing to blink. When the progress bar reaches 100%, both LED[2] and LED[3] blink slower.
  16. Repeat the above steps to dynamically re-program just the child PR region, or both the parent and child PR regions simultaneously.
Figure 14. Programming the Intel Agilex® 7 FPGA Development Board

If you face any PR programming errors, refer to the Avoiding PR Programming Errors section in the Partial Reconfiguration User Guide.


Section Content
Programming the Child PR Region

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