AN 954: Hierarchical Partial Reconfiguration Tutorial: for the Intel Agilex® 7 FPGA Development Board

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ID 683687
Date 1/16/2024
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Document Table of Contents x
Answers to Top FAQs Hierarchical Partial Reconfiguration Tutorial for the Intel Agilex® 7 FPGA Development Board
Hierarchical Partial Reconfiguration Tutorial for the Intel Agilex® 7 FPGA Development Board x
Reference Design Overview Reference Design Requirements Reference Design Files Reference Design Walkthrough Document Revision History for AN 954: Hierarchical Partial Reconfiguration Tutorial for Intel Agilex® 7 FPGA Development Board
Reference Design Walkthrough x
Step 1: Getting Started Step 2: Creating a Child Level Submodule Step 3: Creating Design Partitions Step 4: Allocating Placement and Routing Region for PR Partitions Step 5: Defining Personas Step 6: Creating Revisions Step 7: Compiling the Base Revision Step 8: Preparing the PR Implementation Revisions for Parent PR Partition Step 9: Preparing the PR Implementation Revisions for Child PR Partitions Step 10: Programming the Board Modifying an Existing Persona Adding a New Persona to the Design
Step 6: Creating Revisions x
Setting the Base Revision Type Creating Implementation Revisions
Step 10: Programming the Board x
Programming the Child PR Region
Answers to Top FAQs
Hierarchical Partial Reconfiguration Tutorial for the Intel Agilex® 7 FPGA Development Board

Step 2: Creating a Child Level Submodule

To convert the flat design into a hierarchical PR design, you create a child submodule (blinking_led_child.sv) within the parent submodule (blinking_led.sv).
  1. Create a new design file, blinking_led_child.sv, and add the following lines of code to this file:
    `timescale 1 ps / 1 ps
`default_nettype none

module blinking_led_child (

   // clock
   input wire clock,
   input wire [31:0] counter,

   // Control signals for the LEDs
   output wire led_three_on

);
   localparam COUNTER_TAP = 23;
   reg led_three_on_r;

   assign led_three_on   = led_three_on_r;
   
   always_ff @(posedge clock) begin
      led_three_on_r   <= counter[COUNTER_TAP];
   end

endmodule
  2. Modify blinking_led.sv to connect led_two_on to bit 23 of the counter from the static region, and instantiate the blinking_led_child module. blinking_led.sv must appear as follows:
    `timescale 1 ps / 1 ps
`default_nettype none

module blinking_led(
   // clock
   input wire clock,
   input wire [31:0] counter,
   input wire reset,
   // Control signals for the LEDs
   output wire led_two_on,
   output wire led_three_on
);

   localparam COUNTER_TAP = 23;

   reg led_two_on_r;
   assign  led_two_on    = led_two_on_r;
   
   // The counter:
   always_ff @(posedge clock) begin
         led_two_on_r <= counter[COUNTER_TAP];
   end

   blinking_led_child u_blinking_led_child (
         .led_three_on           (led_three_on),
         .counter                (counter),
         .clock                  (clock)
   );

endmodule
  3. Save all files, retaining the Add file to current project option.
  4. Click Processing > Start > Start Analysis & Synthesis
Level Two Title