AN 954: Hierarchical Partial Reconfiguration Tutorial: for the Intel Agilex® 7 FPGA Development Board

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ID 683687
Date 1/16/2024
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Document Table of Contents
Document Table of Contents x
Answers to Top FAQs Hierarchical Partial Reconfiguration Tutorial for the Intel Agilex® 7 FPGA Development Board
Hierarchical Partial Reconfiguration Tutorial for the Intel Agilex® 7 FPGA Development Board x
Reference Design Overview Reference Design Requirements Reference Design Files Reference Design Walkthrough Document Revision History for AN 954: Hierarchical Partial Reconfiguration Tutorial for Intel Agilex® 7 FPGA Development Board
Reference Design Walkthrough x
Step 1: Getting Started Step 2: Creating a Child Level Submodule Step 3: Creating Design Partitions Step 4: Allocating Placement and Routing Region for PR Partitions Step 5: Defining Personas Step 6: Creating Revisions Step 7: Compiling the Base Revision Step 8: Preparing the PR Implementation Revisions for Parent PR Partition Step 9: Preparing the PR Implementation Revisions for Child PR Partitions Step 10: Programming the Board Modifying an Existing Persona Adding a New Persona to the Design
Step 6: Creating Revisions x
Setting the Base Revision Type Creating Implementation Revisions
Step 10: Programming the Board x
Programming the Child PR Region
Answers to Top FAQs
Hierarchical Partial Reconfiguration Tutorial for the Intel Agilex® 7 FPGA Development Board

Reference Design Files

The files required for this tutorial are available in the following location:

https://github.com/intel/fpga-partial-reconfig

To download the files:
  1. Click Clone or download.
  2. Click Download ZIP. Unzip the fpga-partial-reconfig-master.zip file.
  3. To access the reference design, navigate to the appropriate subfolder for your target device:
    • tutorials/agilex7f_pcie_devkit_blinking_led_hpr
    • tutorials/agilex7m_pcie_devkit_blinking_led_hpr
The flat folder consists of the following files:
Table 1.  Reference Design Files
File Name Description
top.sv

Top-level file containing the flat implementation of the design. This module instantiates the blinking_led sub-partition and the top_counter module.

top_counter.sv Top-level 32-bit counter that controls LED[1] directly. The registered output of the counter controls LED[0], and powers LED[2] and LED[3] via the blinking_led module.
blinking_led.sdc

Defines the timing constraints for the project.
blinking_led.sv In this tutorial, you convert this module into a parent PR partition. The module receives the registered output of top_counter module, which controls LED[2] and LED[3].
blinking_led.qpf

Intel® Quartus® Prime project file containing the list of all the revisions in the project.

blinking_led.qsf

Intel® Quartus® Prime settings file containing the assignments and settings for the project.

Note:

The hpr folder contains the complete set of files you create using this application note. Reference these files at any point during the walkthrough.

Figure 2. Reference Design Files
Level Two Title