AN 954: Hierarchical Partial Reconfiguration Tutorial: for the Intel Agilex® 7 FPGA Development Board

Download PDF
ID 683687
Date 1/16/2024
Public
Document Table of Contents
Document Table of Contents x
Answers to Top FAQs Hierarchical Partial Reconfiguration Tutorial for the Intel Agilex® 7 FPGA Development Board
Hierarchical Partial Reconfiguration Tutorial for the Intel Agilex® 7 FPGA Development Board x
Reference Design Overview Reference Design Requirements Reference Design Files Reference Design Walkthrough Document Revision History for AN 954: Hierarchical Partial Reconfiguration Tutorial for Intel Agilex® 7 FPGA Development Board
Reference Design Walkthrough x
Step 1: Getting Started Step 2: Creating a Child Level Submodule Step 3: Creating Design Partitions Step 4: Allocating Placement and Routing Region for PR Partitions Step 5: Defining Personas Step 6: Creating Revisions Step 7: Compiling the Base Revision Step 8: Preparing the PR Implementation Revisions for Parent PR Partition Step 9: Preparing the PR Implementation Revisions for Child PR Partitions Step 10: Programming the Board Modifying an Existing Persona Adding a New Persona to the Design
Step 6: Creating Revisions x
Setting the Base Revision Type Creating Implementation Revisions
Step 10: Programming the Board x
Programming the Child PR Region
Answers to Top FAQs
Hierarchical Partial Reconfiguration Tutorial for the Intel Agilex® 7 FPGA Development Board

Document Revision History for AN 954: Hierarchical Partial Reconfiguration Tutorial for Intel Agilex® 7 FPGA Development Board

Document Version Intel® Quartus® Prime Version Changes
2024.01.16 23.3
  • Added Top FAQs navigation to the cover.
  • Updated to target Intel Agilex® 7 F-Series and M-Series FPGAs.
2021.08.04 21.1 Initial release.
Level Two Title