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4.3.8.1. eCPRI Message Type 0- IQ Data Transfer
4.3.8.2. eCPRI Message Type 1- Bit Sequence Transfer
4.3.8.3. eCPRI Message Type 2- Real Time Control Data
4.3.8.4. eCPRI Message Type 3- Generic Data Transfer
4.3.8.5. eCPRI Message Type 4- Remote Memory Access
4.3.8.6. eCPRI Message Type 5- One-Way Delay Measurement
4.3.8.7. eCPRI Message Type 6- Remote Reset
4.3.8.8. eCPRI Message Type 7- Event Indication
4.3.8.9. eCPRI Message Type 64- 255 Vendor Specific
5.1. Clock Signals
5.2. Power, Reset, and Firewalls Signals
5.3. TX Time of Day Interface
5.4. RX Time of Day Interface
5.5. Interrupt
5.6. Configuration Avalon® Memory-Mapped Interface
5.7. Ethernet MAC Source Interface
5.8. Ethernet MAC Sink Interface
5.9. External ST Source Interface
5.10. External ST Sink Interface
5.11. eCPRI IP Source Interface
5.12. eCPRI IP Sink Interface
5.13. Miscellaneous Interface Signals
5.14. IWF Type 0 eCPRI Interface
5.15. IWF Type 0 CPRI MAC Interface
5.15.1. CPRI 32-bit IQ Data TX Interface
5.15.2. CPRI 64-bit IQ Data TX Interface
5.15.3. CPRI 32-bit Ctrl_AxC TX Interface
5.15.4. CPRI 64-bit Ctrl_AxC TX Interface
5.15.5. CPRI 32-bit Vendor Specific TX Interface
5.15.6. CPRI 64-bit Vendor Specific TX Interface
5.15.7. CPRI 32-bit Real-time Vendor Specific TX Interface
5.15.8. CPRI 64-bit Real-time Vendor Specific TX Interface
5.15.9. CPRI Gigabit Media Independent Interface (GMII)
5.15.10. CPRI IP L1 Control and Status Interface
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1. Introduction
Updated for: |
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Intel® Quartus® Prime Design Suite 23.3 |
IP Version 3.0.0 |
The enhanced Common Public Radio Interface (eCPRI) Intel® FPGA IP core implements the eCPRI specification version 2.0. The eCPRI IP is a front-haul interface protocol for radio base station aimed at connecting the eCPRI Radio Equipment Control (eREC) and the eCPRI Radio Equipment (eRE) via front-haul transport network.
Figure 1. Typical eCPRI Application on Intel® FPGA Devices