eCPRI Intel® FPGA IP User Guide

ID 683685
Date 11/17/2023
Public

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Document Table of Contents

3. IP Parameters

You customize the IP core by specifying parameters in the IP parameter editor.
Table 9.  Parameters: Configuration Tab
Parameter Supported Values Default Setting Description
Transceiver Tile to be used E

F

H

E You can choose:
  • H-tile or E-tile for your Intel® Stratix® 10 device
  • E-tile or F-tile for your Intel® Agilex™ 7 device
Note: This parameter is not present in the Intel® Arria® 10 IP variations.
Data Width 64 64 Primary data bus width.
PTP Timestamp Fingerprint Width 6 to 30 6

This parameter indicates the width for fingerprint ID signal at external sink interfaces. The IP module appends a 2-bits encoding data to differentiate fingerprint responses for both eCPRI and external sink interface packets.

You can find more details in Section 4.2.1 of the user guide.

The valid range for this parameter is from 6 to 30.

For E tiles, the width fixed to 6.

For H/F-Tiles, you can configure the width within the range of 6 to 30.

Protocol Revision 1 1 Specifies eCPRI protocol revision used in eCPRI common header.

This option is grayed out in the current version of the Intel® Quartus® Prime software.

Delay Measurement off

one_step

two_step

one_step Indicates option to support and the operation mode of delay measurement for eCPRI message type 5 delay measurement.

When set to off, the IP does not include the delay measurement logic.

RX external data path FIFO depth 64

128

256

64 Indicates the depth of the RX external data path FIFO.

The actual depth is log2 of the FIFO depth.

Number of External Sink Interface 1, 2 1 Indicates the number of external sink interfaces generated for the user.
External Sink 1 Queue FIFO Depth

64

128

256

64 Indicates the depth of the external sink 1 interface FIFO.

The actual depth is log2 of the FIFO depth.

External Sink 0 Queue FIFO Depth

64

128

256

64 Indicates the depth of the external sink 0 interface FIFO.

The actual depth is log2 of the FIFO depth.

Advance Mapping Mode On

Off

On When you turn on this parameter with the mf_en bit set in eCPRI Common Control register, it allows the mapping of the destination MAC address and VLAN tag CSE to eCPRI message PC_ID field.
Pair with ORAN On

Off

Off Turn on this option to pair your eCPRI Intel® FPGA IP with Intel® O-RAN FPGA IP. You can also pair your eCPRI Intel® FPGA IP with any external vendor O-RAN IP.
Note: When you turn on this parameter, the eCPRI Intel FPGA IP only supports message type 0, 2, and 5.
Streaming On

Off

Off Indicates Ethernet frame size.
When you turn off this parameter, the maximum Ethernet frame size can be 1500 bytes, and when you turn on, the maximum Ethernet frame size can be 9,000 bytes.
Note: When you turn on this parameter, the sink_pkt_size port is available at the Sink Interface of the eCPRI Intel FPGA IP.
Interworking Function (IWF) Support On

Off

Off Turn on this option to connect your eCPRI IP with one CPRI IP node.
The eCPRI Intel FPGA IP currently support IWF Type 0 only. It does not support IWF type 1 and type 2 in current release of the IP.
Note: When you turn on this parameter, the eCPRI Intel FPGA IP supports message type 0, 2, 5, 6 and 7 with IWF function.
Interworking Function (IWF) Type 0 0 Specifies eCPRI IP IWF type configuration. Currently the IP support IWF Type 0 configuration.
Interworking Function (IWF) Number of CPRI 1 1 Specifies the number of CPRI MAC that can connect to IWF.
Remote Memory Access Timer Bit-width 12 12 Specifies bit-width of the request-response sequence timer for the eCPRI message type 4.

This parameter triggers the timeout no memory access response.

One-way Delay Measurement Time Bit-width 16 16 Specifies bit-width of the request-response sequence timer for the eCPRI message type 5,One-way delay measurement.

This parameter triggers the timeout no memory access response.

Remote Reset Timer Bit-width 12 12 Specifies bit-width of the request-response sequence timer for the eCPRI message type 6.

This parameter triggers the timeout no memory access response.

Default MAC Source Address - 0x000000000000 Default MAC source address after cold and soft reset.
Default MAC Destination Address 0 - 0x000000000000 Default MAC destination address 0 after cold and soft reset.
Default MAC Destination Address 1 - 0x000000000000 Default MAC destination address 1 after cold and soft reset.
Default MAC Destination Address 2 - 0x000000000000 Default MAC destination address 2 after cold and soft reset.
Default MAC Destination Address 3 - 0x000000000000 Default MAC destination address 3 after cold and soft reset.
Default MAC Destination Address 4 - 0x000000000000 Default MAC destination address 4 after cold and soft reset.
Default MAC Destination Address 5 - 0x000000000000 Default MAC destination address 5 after cold and soft reset.
Default MAC Destination Address 6 - 0x000000000000 Default MAC destination address 6 after cold and soft reset.
Default MAC Destination Address 7 - 0x000000000000 Default MAC destination address 7 after cold and soft reset.
Default VLAN ID - 0x000 Default VLAN ID after cold and soft reset.
Data Flow Identification MACADDR

VLANID

MACADDR Use MAC Address or VLAN ID for Data Identification.
Packets Arbitration Scheme L2COS

Fixed

Fixed Specifies the TX packets arbitration scheme.
TX Packets Default Priority 0 to 7 7 Indicates the default priority for S/M/other plane packets that doesn’t contain VLAN ID within L2 header.
TX Arbitration Queue 0 Depth 0

32

64

128

256

128 Indicates the TX arbitration queue 0 depth. FIFO width is 8 Bytes.
TX Arbitration Queue 1 Depth 0

32

64

128

256

128 Indicates the TX arbitration queue 1 depth. FIFO width is 8 bytes.
TX Arbitration Queue 2 Depth 0

32

64

128

256

128 Indicates the TX arbitration queue 2 depth. FIFO width is 8 bytes.
TX Arbitration Queue 3 Depth 0

32

64

128

256

128 Indicates the TX arbitration queue 3 depth. FIFO width is 8 bytes.
TX Arbitration Queue 4 Depth 0

32

64

128

256

128 Indicates the TX arbitration queue 4 depth. FIFO width is 8 bytes.
TX Arbitration Queue 5 Depth 0

32

64

128

256

128 Indicates the TX arbitration queue 5 depth. FIFO width is 8 bytes.
TX Arbitration Queue 6 Depth 0

32

64

128

256

128 Indicates the TX arbitration queue 6 depth. FIFO width is 8 bytes.
TX Arbitration Queue 7 Depth 32

64

128

256

128 Indicates the TX arbitration queue 7 depth. FIFO width is 8 bytes.
For parameters in the Example Design tab, refer to the eCPRI Intel Stratix 10 FPGA Design Example User Guide.