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1. Intel® Agilex™ Configuration User Guide
2. Intel® Agilex™ Configuration Details
3. Intel® Agilex™ Configuration Schemes
4. Including the Reset Release Intel® FPGA IP in Your Design
5. Remote System Update (RSU)
6. Intel® Agilex™ Configuration Features
7. Intel® Agilex™ Debugging Guide
8. Intel® Agilex™ Configuration User Guide Archives
9. Document Revision History for the Intel® Agilex™ Configuration User Guide
2.1. Intel® Agilex™ Configuration Timing Diagram
2.2. Configuration Flow Diagram
2.3. Device Response to Configuration and Reset Events
2.4. Additional Clock Requirements for HPS and Transceivers
2.5. Intel® Agilex™ Configuration Pins
2.6. Configuration Clocks
2.7. Intel® Agilex™ Configuration Time Estimation
2.8. Generating Compressed .sof File
3.1.1. Avalon® -ST Configuration Scheme Hardware Components and File Types
3.1.2. Enabling Avalon-ST Device Configuration
3.1.3. The AVST_READY Signal
3.1.4. RBF Configuration File Format
3.1.5. Avalon-ST Single-Device Configuration
3.1.6. Debugging Guidelines for the Avalon® -ST Configuration Scheme
3.1.7. IP for Use with the Avalon® -ST Configuration Scheme: Intel FPGA Parallel Flash Loader II IP Core
3.1.7.4.1. PFL II IP Recommended Design Constraints to FPGA Avalon-ST Pins
3.1.7.4.2. PFL II IP Recommended Design Constraints for Using QSPI Flash
3.1.7.4.3. PFL II IP Recommended Design Constraints for using CFI Flash
3.1.7.4.4. PFL II IP Recommended Constraints for Other Input Pins
3.1.7.4.5. PFL II IP Recommended Constraints for Other Output Pins
3.2.1. AS Configuration Scheme Hardware Components and File Types
3.2.2. AS Single-Device Configuration
3.2.3. AS Using Multiple Serial Flash Devices
3.2.4. AS Configuration Timing Parameters
3.2.5. Maximum Allowable External AS_DATA Pin Skew Delay Guidelines
3.2.6. Programming Serial Flash Devices
3.2.7. Serial Flash Memory Layout
3.2.8. AS_CLK
3.2.9. Active Serial Configuration Software Settings
3.2.10. Intel® Quartus® Prime Programming Steps
3.2.11. Debugging Guidelines for the AS Configuration Scheme
5.1. Remote System Update Functional Description
5.2. Guidelines for Performing Remote System Update Functions for Non-HPS
5.3. Commands and Responses
5.4. Quad SPI Flash Layout
5.5. Generating Remote System Update Image Files Using the Programming File Generator
5.6. Remote System Update from FPGA Core Example
5.6.1. Prerequisites
5.6.2. Creating Initial Flash Image Containing Bitstreams for Factory Image and One Application Image
5.6.3. Programming Flash Memory with the Initial Remote System Update Image
5.6.4. Reconfiguring the Device with an Application or Factory Image
5.6.5. Adding an Application Image
5.6.6. Removing an Application Image
7.1. Configuration Debugging Checklist
7.2. Intel® Agilex™ Configuration Architecture Overview
7.3. Understanding Configuration Status Using quartus_pgm command
7.4. Configuration File Format Differences
7.5. Understanding SEUs
7.6. Reading the Unique 64-Bit CHIP ID
7.7. E-Tile Transceivers May Fail To Configure
7.8. Understanding and Troubleshooting Configuration Pin Behavior
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2.7. Intel® Agilex™ Configuration Time Estimation
This section describes configuration time for various configuration modes for different bitstream sizes. For example, in PCIe* designs, your system software may require the Intel® Agilex™ device to enter user mode in less than 1 second to return a successful completion status for a valid configuration request. Use the values referenced below to determine the configuration mode that best suits your design requirements.
The table provides time estimates for the full FPGA configuration only. In HPS enabled designs, the table also considers the FPGA configuration first mode. Note that the HPS boot first mode in HPS enabled designs is not considered. Also, the CvP periphery image configuration is not considered. In general, if you use the Micron flash device for AS x4 configuration, the CvP periphery image configuration time is expected to be less than 100 ms.
The following conditions were used to estimate the configuration time values:
- Set the VID mode of operation to PMBus Master mode
- Use Intersil ISL68137 regulator to regulate the PMBus
- Set configuration clock source to OSC_CLK_1 with 25/100/125 MHz
- No advanced security features were enabled
- For AVST x8/x16/x32 configuration modes, set the AVST_CLK to 125 MHz. The external host controller supplies the AVST_DATA by asserting the AVST_VALID signal high whenever the AVST_READY signal is high.
- For AS x4 configuration mode, set the AS_CLK to 166 MHz. Use a Micron device with a 2 Gb density range QSPI flash memory.
Device | Bitstream File Size (MB) | Configuration Time Estimation (ms) | |||
---|---|---|---|---|---|
AS x4 7 | AVST x8 | AVST x16 | AVST x32 | ||
AGF 012 AGF 014 |
2.5 | 250 | 160 | 150 | N/A |
26 | 590 | 340 | 250 | N/A | |
33 | 700 | 390 | 280 | N/A | |
AGI 022 AGI 027 |
3.6 | 320 | 210 | 190 | N/A |
28 | 690 | 390 | 280 | N/A | |
61 | 1,200 | 640 | 420 | N/A |
7 For non-Micron QSPI flash memory, the AS x4 configuration time increases by 126 ms.