Intel® Agilex™ Configuration User Guide

ID 683673
Date 1/14/2022
Public

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3.1. Avalon-ST Configuration

The Avalon® -ST configuration scheme replaces the FPP mode available in earlier device families. Avalon® -ST is the fastest configuration scheme for Intel® Agilex™ devices. This scheme uses an external host, such as a microprocessor, MAX® II, MAX® V, or Intel® MAX® 10 device to drive configuration. The external host controls the transfer of configuration data from external storage such as flash memory to the FPGA. The logic that controls the configuration process resides in the external host. You can use the PFL II IP with a MAX® II, MAX® V, or Intel® MAX® 10 device as the host to read configuration data from the flash memory device and configure the Intel® Agilex™ device. The Avalon® -ST configuration scheme is called passive because the external host, not the Intel® Agilex™ device, controls configuration.

Table 14.   Avalon® -ST Configuration Data Width, Clock Rates, and Data RatesMbps is an abbreviation for Megabits per second.
Protocol Data Width (bits) Max Clock Rate Max Data Rate MSEL[2:0]
Avalon® -ST 32 125 MHz 4000 Mbps 000
16 125 MHz 2000 Mbps 101
8 125 MHz 1000 Mbps 110
Table 15.  Required Configuration Signals for the Avalon® -ST Configuration Scheme You can use an 8-, 16-, or 32-bit Avalon-ST configuration data bus. You specify SDM I/O pin functions using the Device > Device and Pin Options > Configuration dialog box in the Intel® Quartus® Prime software. For the Avalon-ST x16 and x32 configuration, you can reassign the GPIO, dual-purpose configuration pins for other functions in user mode using the Device > Device and Pin Options > Dual-Purpose Pins dialog box.
Signal Name Pin Type Direction Powered by
nSTATUS SDM I/O Output VCCIO_SDM
nCONFIG SDM I/O Input VCCIO_SDM
MSEL[2:0] SDM I/O Input VCCIO_SDM
CONF_DONE 8 SDM I/O Output VCCIO_SDM
AVSTx8_READY SDM I/O Output VCCIO_SDM
AVST_READY GPIO, Dual-Purpose Output VCCIO
AVSTx8_DATA[7:0] SDM I/O Input VCCIO_SDM
AVSTx8_VALID SDM I/O Input VCCIO_SDM
AVSTx8_CLK SDM I/O Input VCCIO_SDM
AVST_DATA[31:0] GPIO, Dual-Purpose Input VCCIO
AVST_VALID GPIO, Dual-Purpose Input VCCIO
AVST_CLK GPIO, Dual-Purpose Input VCCIO

Refer to the Intel® Agilex™ Data Sheet for configuration timing estimates.

The x16 and x32 modes use GPIO pins that only support the 1.2 V I/O standard. The SDM I/O pins require a 1.8 V power supply. Consequently, you may need a voltage-level translation between the FPGA and external host because of some signals, to accommodate both power requirements.
Attention: Access to the I/O pins located in bank 3A with pin index[91...95] is not allowed for the AVSTx16 or x32 configuration scheme. You must leave these pins unconnected. For more information, refer to the device pin mapping files to identify the exact pin location.
Note: Although the INIT_DONE configuration signal is not required for configuration, Intel recommends that you use this signal. The SDM drives the INIT_DONE signal high to indicate the device is fully in user mode. This signal is important when debugging configuration.
Note: If you create custom logic instead of using the PFL II IP to drive configuration, refer to the Avalon Streaming Interfaces in the Avalon Interface Specifications for protocol details.
8 CONF_DONE is required if you are using the Intel FPGA Parallel Flash Loader II IP as the configuration host.