Visible to Intel only — GUID: sss1440053786922
Ixiasoft
Visible to Intel only — GUID: sss1440053786922
Ixiasoft
3.1. Avalon-ST Configuration
The Avalon® -ST configuration scheme replaces the FPP mode available in earlier device families. Avalon® -ST is the fastest configuration scheme for Intel® Agilex™ devices. This scheme uses an external host, such as a microprocessor, MAX® II, MAX® V, or Intel® MAX® 10 device to drive configuration. The external host controls the transfer of configuration data from external storage such as flash memory to the FPGA. The logic that controls the configuration process resides in the external host. You can use the PFL II IP with a MAX® II, MAX® V, or Intel® MAX® 10 device as the host to read configuration data from the flash memory device and configure the Intel® Agilex™ device. The Avalon® -ST configuration scheme is called passive because the external host, not the Intel® Agilex™ device, controls configuration.
Protocol | Data Width (bits) | Max Clock Rate | Max Data Rate | MSEL[2:0] |
---|---|---|---|---|
Avalon® -ST | 32 | 125 MHz | 4000 Mbps | 000 |
16 | 125 MHz | 2000 Mbps | 101 | |
8 | 125 MHz | 1000 Mbps | 110 |
Signal Name | Pin Type | Direction | Powered by |
---|---|---|---|
nSTATUS | SDM I/O | Output | VCCIO_SDM |
nCONFIG | SDM I/O | Input | VCCIO_SDM |
MSEL[2:0] | SDM I/O | Input | VCCIO_SDM |
CONF_DONE 8 | SDM I/O | Output | VCCIO_SDM |
AVSTx8_READY | SDM I/O | Output | VCCIO_SDM |
AVST_READY | GPIO, Dual-Purpose | Output | VCCIO |
AVSTx8_DATA[7:0] | SDM I/O | Input | VCCIO_SDM |
AVSTx8_VALID | SDM I/O | Input | VCCIO_SDM |
AVSTx8_CLK | SDM I/O | Input | VCCIO_SDM |
AVST_DATA[31:0] | GPIO, Dual-Purpose | Input | VCCIO |
AVST_VALID | GPIO, Dual-Purpose | Input | VCCIO |
AVST_CLK | GPIO, Dual-Purpose | Input | VCCIO |
Refer to the Intel® Agilex™ Data Sheet for configuration timing estimates.
- Avalon -ST Configuration Scheme Hardware Components and File Types
- Enabling Avalon-ST Device Configuration
- The AVST_READY Signal
- RBF Configuration File Format
- Avalon-ST Single-Device Configuration
- Debugging Guidelines for the Avalon -ST Configuration Scheme
- IP for Use with the Avalon -ST Configuration Scheme: Intel FPGA Parallel Flash Loader II IP Core