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Visible to Intel only — GUID: bjj1534517451738
Ixiasoft
2.4. Additional Clock Requirements for HPS and Transceivers
FPGA Configuration
To avoid configuration failures, the Intel® Agilex™ device requires additional clocks for transceivers, HPS EMIF IP, and all E-tile variants. You must provide a free-running, stable reference clock to these blocks before configuration begins. The clock frequencies must match the frequency settings specified in the Intel® Quartus® Prime software during configuration. This reference clock is in addition to the configuration clock requirements for an internal or external oscillator described in OSC_CLK_1 Requirements.
- HPS reference clock: HPS_OSC_CLK, when HPS enabled 3
- HPS EMIF: pll_ref_clk
- E-tile transceivers: REFCLK_GXE
Intel® Quartus® Prime Pro Edition software allows you to configure the HPS prior to FPGA configuration. To enable this option, select HPS First in the Assignments > Device > Device and Pin Options > Configuration > HPS/FPGA Configuration order dialog box.
HPS First Configuration
- HPS reference clock: HPS_OSC_CLK
- HPS EMIF (when in use): pll_ref_clk
- E-tile transceivers: REFCLK_GXE
The remaining clocks specified in the FPGA Configuration must be fully operational prior the FPGA core logic configuration, also called phase 2 configuration.