5G LDPC-V Intel® FPGA IP User Guide

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ID 683670
Date 12/12/2022
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Document Table of Contents
Document Table of Contents x
1. About the 5G LDPC-V Intel® FPGA IP 2. Getting Started with the Intel® FPGA IP 3. Designing with the 5G LDPC-V Intel® FPGA IP 4. 5G LDPC-V Intel® FPGA IP Functional Description 5. 5G LPDC-V IP User Guide Archive 6. Document Revision History for the 5G LDPC-V Intel® FPGA IP User Guide
1. About the 5G LDPC-V Intel® FPGA IP x
1.1. 5G LDPC-V Intel® FPGA IP Features 1.2. 5G LDPC-V Intel® FPGA IP Device Family Support 1.3. Release Information for the 5G LDPC-V Intel® FPGA IP 1.4. 5G LDPC-V Performance and Resources
2. Getting Started with the Intel® FPGA IP x
2.1. Installing and Licensing Intel® FPGA IP Cores
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode 2.1.2. 5G LDPC-V IP Timeout Behavior
3. Designing with the 5G LDPC-V Intel® FPGA IP x
3.1. 5G LDPC-V IP Directory Structure 3.2. Generating a 5G LPDC-V IP 3.3. Simulating the 5G LDPC-V IP 3.4. 5G LDPC-V Simulation Results
3.2. Generating a 5G LPDC-V IP x
3.2.1. 5G LDPC-V IP Parameters
4. 5G LDPC-V Intel® FPGA IP Functional Description x
4.1. 5G LDPC-V Transmitter Functional Description 4.2. 5G LDPC-V Receiver Functional Description 4.3. Avalon Streaming Interfaces in DSP Intel FPGA IP 4.4. 5G LDPC-V Throughput and Latency
4.1. 5G LDPC-V Transmitter Functional Description x
4.1.1. 5G LDPC-V Transmitter Signals 4.1.2. 5G LDPC-V Lifting Factor and Code Rate Indexes
4.2. 5G LDPC-V Receiver Functional Description x
4.2.1. 5G LDPC-V Receiver Signals
1. About the 5G LDPC-V Intel® FPGA IP
2. Getting Started with the Intel® FPGA IP
3. Designing with the 5G LDPC-V Intel® FPGA IP
4. 5G LDPC-V Intel® FPGA IP Functional Description
5. 5G LPDC-V IP User Guide Archive
6. Document Revision History for the 5G LDPC-V Intel® FPGA IP User Guide

6. Document Revision History for the 5G LDPC-V Intel® FPGA IP User Guide

Date IP Version Intel® Quartus® Prime Software Version Changes
2022.12.12 5.0.0 22.4
  • Added two new parameters:
    • Dual Decoder, LDPC2 Zmax = 192 using DSP
    • Single Decoder, Standard using DSP.
  • Removed Dual Decoder, LDPC2 Zmax = 128 and Dual Decoder, LDPC2 Zmax = 96. Previous designs using this parameter can now use Zmax = 192 as the substitute.
  • Updated Performance and Resources
  • Added ordering code
  • Corrected data in Transmitter Throughput table
2022.03.30 4.0.0 22.1
  • Changed /sim directory files.
  • Removed LLR input width parameter.
  • Added LITE_COEFF and DECODER_LITE parameters
  • Added another Decoder Throughput and Latency table.
  • Updated Performance and Resource Utilization tables
2021.07.19 3.0.0 21.2
  • Deleted LDPC-V Requirements and LDPC-V Limitaitons
  • Updated performance table
  • Added two new parameters
  • Updated signal descriptions:
    • i_ldpc_paras
    • i_source_ready
  • Updated various receiver signal descriptions
  • Removed some entries in Throughput and Latency table
2020.08.19 2.0.0 20.2
  • Corrected version to 20.2
  • Corrected performance table
2020.06.30 2.0.0 20.1
  • Corrected descriptions for:
    • avmm_address
    • avmm_readdata
    • avmm_writedata
  • Added new device to Performance and Resource Utilization
2020.06.02 2.0.0 20.1
  • Removed derate matcher, HARQ, and decoder signal tables.
  • Removed code block CRC, encoder, and rate matcher signal tables,
  • Corrected and added signals to Receiver Top-Level Signals table
  • Added Throughput and Latency.
  • Added Performance and Resource Utilization
  • Added support for Intel® Agilex™ devices
  • Updated simulation timing diagrams
  • Added IP Requirements and IP Limitations.
  • Removed second decoder option parameter.
2019.09.02 0.1.0 19.2 Corrected 5G LDPC-V block diagram.
2019.08.30 0.1.0 19.2 Initial release.
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