AN 903: Accelerating Timing Closure: in Intel® Quartus® Prime Pro Edition

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ID 683664
Date 2/25/2021
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Document Table of Contents x
1. AN 903: Accelerating Timing Closure in Intel® Quartus® Prime Pro Edition
1. AN 903: Accelerating Timing Closure in Intel® Quartus® Prime Pro Edition x
1.1. Step 1: Analyze and Optimize Design RTL 1.2. Step 2: Apply Compiler Optimization Techniques 1.3. Step 3: Preserve Satisfactory Results 1.4. AN 903 Document Revision History
1.1. Step 1: Analyze and Optimize Design RTL x
1.1.1. Correct Design Assistant Violations 1.1.2. Reduce Logic Levels 1.1.3. Reduce High Fan-Out Nets
1.2. Step 2: Apply Compiler Optimization Techniques x
1.2.1. Apply Compiler Optimization Modes and Strategies 1.2.2. Reduce Congestion for High Utilization
1.2.2. Reduce Congestion for High Utilization x
1.2.2.1. Experiment with Area and Routability Options 1.2.2.2. Consider Fractal Synthesis for Arithmetic-Intensive Designs
1.2.2.2. Consider Fractal Synthesis for Arithmetic-Intensive Designs x
1.2.2.2.1. Enabling or Disabling Fractal Synthesis
1.3. Step 3: Preserve Satisfactory Results x
1.3.1. Lock Down Clocks, RAMs, and DSPs 1.3.2. Preserve Design Partition Results
1.3.2. Preserve Design Partition Results x
1.3.2.1. Design Partition Settings
1. AN 903: Accelerating Timing Closure in Intel® Quartus® Prime Pro Edition

1.3.2. Preserve Design Partition Results

After partitioning the design, you can preserve the partitions for blocks that meet timing, and focus optimization on the other design blocks. In addition, the Fast Preserve option simplifies the logic of a preserved partition to only interface logic during compilation, thereby reducing the compilation time for the partition.
Note: Fast Preserve only supports root partition reuse and partial reconfiguration designs.
For designs with sub-modules that are challenging for timing closure, you can perform stand-alone optimization and compilation of the module's partition, and then export the timing-closed module to preserve the implementation in subsequent compilations.
Preserving Design Partition Results

Block-based design requires design partitioning. Design partitioning allows you to preserve individual logic blocks in your design, but can also introduce potential performance loss due to partition crossing and floorplan effects. You need to balance these factors when using block-based design techniques.

The following high level steps describe the partition preservation flow for root partition reuse designs:

  1. Click Processing > Start > Start Analysis & Elaboration.
  2. In the Project Navigator, right-click the timing closed design instance, point to Design Partition, and select a partition Type, as Design Partition Settings describes.
    Figure 19. Create Design Partitions
  3. Define Logic Lock floorplanning constraints for the partition. In the Design Partitions Window, right-click the partition and then click Logic Lock Region > Create New Logic Lock Region. Ensure that the region is large enough to enclose all logic in the partition.
  4. To export the partition results following compilation, in the Design Partitions Window, specify the partition .qdb as the Post Final Export File.
    Figure 20. Post Final Export File
  5. To compile the design and export the partition, click Compile Design on the Compilation Dashboard.
  6. Open the top-level project in the Intel® Quartus® Prime software.
  7. Click Assignments > Settings > Compiler Settings > Incremental Compile. Turn on the Fast Preserve option.
    Figure 21. Fast Preserve Option
  8. Click OK.
  9. In the Design Partitions Window, specify the exported .qdb as the Partition Database File for the partition in question. This .qdb is now the source for this partition in the project. When you enable the Fast Preserve option, the Compiler reduces the logic of the imported partition to only interface logic, thereby reducing the compilation time the partition requires.
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