AN 903: Accelerating Timing Closure: in Intel® Quartus® Prime Pro Edition

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ID 683664
Date 2/25/2021
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Document Table of Contents
Document Table of Contents x
1. AN 903: Accelerating Timing Closure in Intel® Quartus® Prime Pro Edition
1. AN 903: Accelerating Timing Closure in Intel® Quartus® Prime Pro Edition x
1.1. Step 1: Analyze and Optimize Design RTL 1.2. Step 2: Apply Compiler Optimization Techniques 1.3. Step 3: Preserve Satisfactory Results 1.4. AN 903 Document Revision History
1.1. Step 1: Analyze and Optimize Design RTL x
1.1.1. Correct Design Assistant Violations 1.1.2. Reduce Logic Levels 1.1.3. Reduce High Fan-Out Nets
1.2. Step 2: Apply Compiler Optimization Techniques x
1.2.1. Apply Compiler Optimization Modes and Strategies Experiment with Compiler Optimization Mode Settings Design Space Explorer II Compilation Strategies 1.2.2. Reduce Congestion for High Utilization
1.2.2. Reduce Congestion for High Utilization x
1.2.2.1. Experiment with Area and Routability Options 1.2.2.2. Consider Fractal Synthesis for Arithmetic-Intensive Designs
1.2.2.2. Consider Fractal Synthesis for Arithmetic-Intensive Designs x
1.2.2.2.1. Enabling or Disabling Fractal Synthesis
1.3. Step 3: Preserve Satisfactory Results x
1.3.1. Lock Down Clocks, RAMs, and DSPs 1.3.2. Preserve Design Partition Results
1.3.2. Preserve Design Partition Results x
1.3.2.1. Design Partition Settings
1. AN 903: Accelerating Timing Closure in Intel® Quartus® Prime Pro Edition

1.2.1. Apply Compiler Optimization Modes and Strategies

Use the following information to apply Compiler optimization modes and Design Space Explorer II (DSE II) compilation strategies.

Experiment with Compiler Optimization Mode Settings

Follow these steps to experiment with Compiler optimization mode settings:

  1. Create or open an Intel® Quartus® Prime project.
  2. To specify the Compiler's high-level optimization strategy, click Assignments > Settings > Compiler Settings. Experiment with any of the following mode settings, as Table 3 describes.
  3. To compile the design with these settings, click Start Compilation on the Compilation Dashboard.
  4. View the compilation results in the Compilation Report.
  5. Click Tools > Timing Analyzer to view the results of optimization settings on performance.
Figure 12. Compiler Optimization Mode Settings
Table 3.  Optimization Modes (Compiler Settings Page)

Optimization Mode

Description

Balanced (normal flow)

The Compiler optimizes synthesis for balanced implementation that respects timing constraints.

High Performance Effort

The Compiler increases the timing optimization effort during placement and routing, and enables timing-related Physical Synthesis optimizations (per register optimization settings). Each additional optimization can increase compilation time.

High Performance with Maximum Placement Effort Enables the same Compiler optimizations as High Performance Effort, with additional placement optimization effort.
Superior Performance Enables the same Compiler optimizations as High Performance Effort, and adds more optimizations during Analysis & Synthesis to maximize design performance with a potential increase to logic area. If design utilization is already very high, this option may lead to difficulty in fitting, which can also negatively affect overall optimization quality.
Superior Performance with Maximum Placement Effort Enables the same Compiler optimizations as Superior Performance, with additional placement optimization effort.

Aggressive Area

The Compiler makes aggressive effort to reduce the device area required to implement the design at the potential expense of design performance.

High Placement Routability Effort The Compiler makes high effort to route the design at the potential expense of design area, performance, and compilation time. The Compiler spends additional time reducing routing utilization, which can improve routability and also saves dynamic power.
High Packing Routability Effort The Compiler makes high effort to route the design at the potential expense of design area, performance, and compilation time. The Compiler spends additional time packing registers, which can improve routability and also saves dynamic power.
Optimize Netlist for Routability The Compiler implements netlist modifications to increase routability at the possible expense of performance.

High Power Effort

The Compiler makes high effort to optimize synthesis for low power. High Power Effort increases synthesis run time.

Aggressive Power

Makes aggressive effort to optimize synthesis for low power. The Compiler further reduces the routing usage of signals with the highest specified or estimated toggle rates, saving additional dynamic power but potentially affecting performance.

Aggressive Compile Time

Reduces the compile time required to implement the design with reduced effort and fewer performance optimizations. This option also disables some detailed reporting functions.

Note: Turning on Aggressive Compile Time enables Intel® Quartus® Prime Settings File (.qsf) settings which cannot be overridden by other .qsf settings.

Design Space Explorer II Compilation Strategies

DSE II allows you to find optimal project settings for resource, performance, or power optimization goals. DSE II allows you to iteratively compile a design using different preset combinations of settings and constraints to achieve a specific goal. DSE II then reports the best settings combination to meet your goals. DSE II can also take advantage of parallelization abilities to compile seeds on multiple computers. DSE II Compilation Strategy settings echo the Optimization Mode settings in Table 3

Figure 13. Design Space Explorer II

Follow these steps to specify Compilation Strategy for DSE II:

  1. To launch DSE II (and close the Intel® Quartus® Prime software), click Tools > Launch Design Space Explorer II. DSE II opens after the Intel® Quartus® Prime software closes.
  2. On the DSE II toolbar, click the Exploration icon.
  3. Expand Exploration Points.
  4. Select Design exploration. Enable any of the Compilation strategies to run design explorations targeting those strategies.
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