1.1.1. Correct Design Assistant Violations
You can run Design Assistant in Compilation Flow mode, allowing you to view the violations relevant for the compilation stages you run. Alternatively, Design Assistant is available in analysis mode in the Timing Analyzer and Chip Planner.
- Compilation Flow Mode—runs automatically during one or more stages of compilation. In this mode, Design Assistant utilizes in-flow (transient) data during compilation.
- Analysis Mode—run Design Assistant from Timing Analyzer and Chip Planner to analyze design violations at a specific compilation stage, before moving forward in the compilation flow. In analysis mode, Design Assistant uses static compilation snapshot data.
Design Assistant designates each rule violation with one of the following severity levels. You can specify which rules you want the Design Assistant to check in your design, and customize the severity levels, thus eliminating rule checks that are not important for your design.
Categories | Description | Severity Level Color |
---|---|---|
Critical | Address issue for hand-off. | Red |
High | Potentially causes functional failure. May indicate missing or incorrect design data. | Orange |
Medium | Potentially impacts quality of results for fMAX or resource utilization. | Brown |
Low | Rule reflects best practices for RTL coding guidelines. | Blue |
Setting Up Design Assistant
You can fully customize the Design Assistant for your individual design characteristics and reporting requirements. Click
to specify options that control which rules and parameters apply to the various stages of design compilation for design rule checking.Running Design Assistant
When enabled, the Design Assistant runs automatically during compilation and reports enabled design rule violations in the Compilation Report. Alternatively, you can run Design Assistant in Analysis Mode on a specific compilation snapshot to focus analysis on only that stage.
To enable automated Design Assistant checking during compilation:
- Turn on Enable Design Assistant execution during compilation in the Design Assistant Rule Settings.
To run Design Assistant in analysis mode to validate a specific snapshot against any design rules that apply to the snapshot:
- Click Report DRC in the Timing Analyzer or Chip Planner Tasks panel.
Viewing and Correcting Design Assistant Results
The Design Assistant reports enabled design rule violations in the various stages of the Compilation Report.
Modify your RTL to correct the design rule violations.