6.4. Transceiver Reconfiguration Signals
Name | Width | Direction | Clock Domain | Description |
---|---|---|---|---|
phy_reconfig_read |
N/2 (PAM4 mode) N (NRZ mode) |
Input | reconfig_clk | PCS reconfiguration read command signals. |
phy_reconfig_write |
N/2 (PAM4 mode) N (NRZ mode) |
Input | reconfig_clk | PCS reconfiguration write command signals. |
phy_reconfig_address |
21*(N/2) (PAM4 mode) 19*N (NRZ mode) |
Input | reconfig_clk | Specifies PCS reconfiguration Avalon memory-mapped interface address in a selected lane. For NRZ mode, each lane has 19 bits and lane 0 address starts from phy_reconfig_address[18:0].
Example, for a 4-lane NRZ design:
For PAM4 mode, the lower 19 bits within the 21-bit bus specify the address and the upper 2 bits specify the lane.
Example, for a 4-lane PAM4 design:
|
phy_reconfig_readdata |
32*(N/2) 32*N (NRZ mode) |
Output | reconfig_clk | Specifies PCS reconfiguration data to be read by a ready cycle in a selected lane. |
phy_reconfig_waitrequest |
N/2 (PAM4 mode) N (NRZ mode) |
Output | reconfig_clk | Represents PCS reconfiguration Avalon memory-mapped interface stalling signal in a selected lane. |
phy_reconfig_writedata | 32*(N/2) (PAM4 mode) 32*N (NRZ mode) |
Input | reconfig_clk | Specifies PCS reconfiguration data to be written on a write cycle in a selected lane. |
phy_reconfig_readdata_valid | N/2 (PAM4 mode) N (NRZ mode) |
Output | reconfig_clk | Specifies PCS reconfiguration received data is valid in a selected lane. |
Name | Width | Direction | Clock Domain | Description |
---|---|---|---|---|
xcvr_reconfig_read | N*2 (PAM4 mode) N (NRZ mode) |
Input | reconfig_clk | PMA reconfiguration read command signals. |
xcvr_reconfig_write | N*2 (PAM4 mode) N (NRZ mode) |
Input | reconfig_clk | PMA reconfiguration write command signals. |
xcvr_reconfig_address | 19*N*2 (PAM4 mode) 19*N (NRZ mode) |
Input | reconfig_clk | Specifies PMA Avalon memory-mapped interface address in a selected lane. In both PAM4 ad NRZ modes, each lane has 19 bits and lane 0 address starts from xcvr_reconfig_address[18:0].
Example, for a 4-lane design:
|
xcvr_reconfig_readdata | 8*N*2 (PAM4 mode) 8*N (NRZ mode) |
Output | reconfig_clk | Specifies PMA data to be read by a ready cycle in a selected lane. |
xcvr_reconfig_waitrequest | N*2 (PAM4 mode) N (NRZ mode) |
Output | reconfig_clk | Represents PMA Avalon memory-mapped interface stalling signal in a selected lane. |
xcvr_reconfig_writedata | 8*N*2 (PAM4 mode) 8*N (NRZ mode) |
Input | reconfig_clk | Specifies PMA data to be written on a write cycle in a selected lane. |
Name | Width | Direction | Clock Domain | Description |
---|---|---|---|---|
rsfec_reconfig_read | 1 | Input | reconfig_clk | RS-FEC reconfiguration read command signal. |
rsfec_reconfig_write | 1 | Input | reconfig_clk | RS-FEC reconfiguration write command signal. |
rsfec_reconfig_address | 11 + lane offset |
Input | reconfig_clk | Specifies RS-FEC reconfiguration Avalon memory-mapped interface address.
For PAM4 mode:
For NRZ mode:
|
rsfec_reconfig_readdata | 8 | Output | reconfig_clk | Specifies RS-FEC reconfiguration data to be read by a ready cycle in a selected lane. |
rsfec_reconfig_waitrequest | 1 | Output | reconfig_clk | Represents RS-FEC reconfiguration Avalon memory-mapped interface stalling signal in a selected lane. |
rsfec_reconfig_writedata | 8 | Input | reconfig_clk | Specifies RS-FEC reconfiguration data to be written on a write cycle in a selected lane. |