Serial Lite IV Intel® FPGA IP User Guide

Download PDF
ID 683655
Date 10/02/2023
Public
Document Table of Contents
Document Table of Contents x
1. About the Serial Lite IV Intel® FPGA IP User Guide 2. Serial Lite IV Intel® FPGA IP Overview 3. Functional Description 4. Getting Started 5. Parameters 6. Serial Lite IV Intel® FPGA IP Interface Signals 7. Designing with Serial Lite IV Intel® FPGA IP 8. Serial Lite IV Intel® FPGA IP Registers 9. Serial Lite IV Intel® FPGA IP User Guide Archives 10. Document Revision History for the Serial Lite IV Intel® FPGA IP User Guide
2. Serial Lite IV Intel® FPGA IP Overview x
2.1. Release Information 2.2. Supported Features 2.3. IP Version Support Level 2.4. Device Speed Grade Support 2.5. Resource Utilization and Latency 2.6. Bandwidth Efficiency
3. Functional Description x
3.1. TX Datapath 3.2. RX Datapath 3.3. Serial Lite IV Intel® FPGA IP Clock Architecture 3.4. Reset and Link Initialization 3.5. Link Rate and Bandwidth Efficiency Calculation
3.1. TX Datapath x
3.1.1. TX MAC Adapter 3.1.2. Control Word (CW) Insertion 3.1.3. TX CRC 3.1.4. TX MII Encoder 3.1.5. TX PCS and PMA
3.1.2. Control Word (CW) Insertion x
3.1.2.1. Start-of-burst CW 3.1.2.2. End-of-burst CW 3.1.2.3. Alignment Paired CW 3.1.2.4. Empty-cycle CW 3.1.2.5. Idle CW 3.1.2.6. Data Word
3.2. RX Datapath x
3.2.1. RX PCS and PMA 3.2.2. RX MII Decoder 3.2.3. RX CRC 3.2.4. RX Deskew 3.2.5. RX CW Removal
3.4. Reset and Link Initialization x
3.4.1. TX Reset and Initialization Sequence 3.4.2. RX Reset and Initialization Sequence 3.4.3. PMA Adaptation Flow
3.4.3. PMA Adaptation Flow x
3.4.3.1. Starting the PMA Adaptation Flow
4. Getting Started x
4.1. Installing and Licensing Intel® FPGA IP Cores 4.2. Specifying the IP Parameters and Options 4.3. Generated File Structure 4.4. Simulating Intel® FPGA IP Cores 4.5. Synthesizing IP Cores in Other EDA Tools 4.6. Compiling the Full Design
4.1. Installing and Licensing Intel® FPGA IP Cores x
4.1.1. Intel® FPGA IP Evaluation Mode
4.4. Simulating Intel® FPGA IP Cores x
4.4.1. Simulating and Verifying the Design
6. Serial Lite IV Intel® FPGA IP Interface Signals x
6.1. Clock Signals 6.2. Reset Signals 6.3. MAC Signals 6.4. Transceiver Reconfiguration Signals 6.5. PMA Signals
7. Designing with Serial Lite IV Intel® FPGA IP x
7.1. Reset Guidelines 7.2. Error Handling Guidelines 7.3. E-Tile Channel Placement Tool
1. About the Serial Lite IV Intel® FPGA IP User Guide
2. Serial Lite IV Intel® FPGA IP Overview
3. Functional Description
4. Getting Started
5. Parameters
6. Serial Lite IV Intel® FPGA IP Interface Signals
7. Designing with Serial Lite IV Intel® FPGA IP
8. Serial Lite IV Intel® FPGA IP Registers
9. Serial Lite IV Intel® FPGA IP User Guide Archives
10. Document Revision History for the Serial Lite IV Intel® FPGA IP User Guide

3.2.5. RX CW Removal

This block decodes the CWs and sends data to the user logic using the Avalon® streaming interface after the removal of the CWs.

When there is no valid data available, the RX CW removal block deasserts the rx_avs_valid signal.

In FULL mode, if the user bit is set, this block asserts the rx_is_usr_cmd signal and the data in the first clock cycle is used as user-defined information or command.

When rx_avs_ready deasserts and rx_avs_valid asserts, the RX CW removal block generates an error condition to the user logic.

The Avalon® streaming signals related to this block are as follow:
  • rx_avs_startofpacket
  • rx_avs_endofpacket
  • rx_avs_channel
  • rx_avs_empty
  • rx_avs_data
  • rx_avs_valid
  • rx_num_valid_bytes_eob
  • rx_is_usr_cmd (only available in Full mode)
Level Two Title