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1. About the Serial Lite IV Intel® FPGA IP User Guide
2. Serial Lite IV Intel® FPGA IP Overview
3. Functional Description
4. Getting Started
5. Parameters
6. Serial Lite IV Intel® FPGA IP Interface Signals
7. Designing with Serial Lite IV Intel® FPGA IP
8. Serial Lite IV Intel® FPGA IP Registers
9. Serial Lite IV Intel® FPGA IP User Guide Archives
10. Document Revision History for the Serial Lite IV Intel® FPGA IP User Guide
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7.1. Reset Guidelines
Follow these reset guidelines to implement your system-level reset.
- Tie tx_pcs_fec_phy_reset_n and rx_pcs_fec_phy_reset_n signals together on the system level in order to reset the TX and RX PCS simultaneously.
- Assert tx_pcs_fec_phy_reset_n, rx_pcs_fec_phy_reset_n, tx_core_rst_n, rx_core_rst_n, and reconfig_reset signals at the same time. Refer to Reset and Link Initialization for more information about the IP reset and initialization sequences.
- Hold tx_pcs_fec_phy_reset_n, and rx_pcs_fec_phy_reset_n signals low, and reconfig_reset signal high for at least 200 ns to properly reset the custom PCS and the reconfiguration blocks.
- To achieve fast link-up between FPGA devices, reset the connected Serial Lite IV Intel® FPGA IPs at the same time. Refer to Serial Lite IV Intel® Stratix® 10 FPGA IP Design Example User Guide for information about monitoring the IP TX and RX link using the toolkit.