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1. About the Serial Lite IV Intel® FPGA IP User Guide
2. Serial Lite IV Intel® FPGA IP Overview
3. Functional Description
4. Getting Started
5. Parameters
6. Serial Lite IV Intel® FPGA IP Interface Signals
7. Designing with Serial Lite IV Intel® FPGA IP
8. Serial Lite IV Intel® FPGA IP Registers
9. Serial Lite IV Intel® FPGA IP User Guide Archives
10. Document Revision History for the Serial Lite IV Intel® FPGA IP User Guide
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3.1.2.5. Idle CW
Figure 12. Idle CW Format
The MAC insert the IDLE CW when there is no transmission. During this period, the tx_avs_valid signal is low.
You can use the IDLE CW when a burst transfer has completed or the transmission is in an idle state.