AN 927: JESD204C Intel® FPGA IP and ADI AD9081 MxFE* ADC Interoperability Report for Intel® Stratix® 10 E-Tile Devices

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ID 683652
Date 9/28/2020
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Document Table of Contents
Document Table of Contents x
1. JESD204C Intel® FPGA IP and ADI AD9081 MxFE* ADC Interoperability Checkout Report for Intel® Stratix® 10 E-tile Devices
1. JESD204C Intel® FPGA IP and ADI AD9081 MxFE* ADC Interoperability Checkout Report for Intel® Stratix® 10 E-tile Devices x
1.1. Hardware Requirements 1.2. Hardware Setup 1.3. Hardware Checkout Methodology 1.4. JESD204C Intel® FPGA IP and ADC Configurations 1.5. Test Results 1.6. Test Result Comments 1.7. Document Revision History for AN 927: JESD204C Intel® FPGA IP and ADI AD9081 MxFE* ADC Interoperability Report for Intel® Stratix® 10 E-Tile Devices 1.8. Appendix
1.3. Hardware Checkout Methodology x
1.3.1. Receiver Data Link Layer 1.3.2. Receiver Transport Layer (TL) 1.3.3. Deterministic Latency - Subclass 1 (DL)
1.3.1. Receiver Data Link Layer x
1.3.1.1. Sync Header Alignment (SHA) 1.3.1.2. Extended Multiblock Alignment (EMBA)
1. JESD204C Intel® FPGA IP and ADI AD9081 MxFE* ADC Interoperability Checkout Report for Intel® Stratix® 10 E-tile Devices

1.3.2. Receiver Transport Layer (TL)

To check the data integrity of the payload data stream through the receiver (RX) JESD204C Intel® FPGA IP and transport layer, the ADC is configured to ramp/PRBS test pattern. The ADC is also set to operate with the same configuration as set in the JESD204C Intel® FPGA IP. The ramp/PRBS checker in the FPGA fabric checks the ramp/PRBS data integrity for one minute. The RX JESD204C Intel® FPGA IP register rx_err is polled continuously for zero value for one minute.

The figure below shows the conceptual test setup for data integrity checking.

Figure 3. Data Integrity Check Using Ramp/PRBS15 Checker
Table 3.  Transport Layer Test Cases
Test Case Objective Description Passing Criteria
TL.1 Check the transport layer mapping of the data channel using ramp test pattern. The following signals in <ip_variant_name> _base.v are tapped:
  • j204c_rx_avst_ready
  • j204c_rx_avst_valid
  • j204c_rx_avst_data [(M*S*WIDTH_MULP*N)-1:0] 2 3 4 5
  • j204c_rx_avst_control [(M*S*WIDTH_MULP*CS)-1:0] 2 3 4 6
  • rx_patchk_data_error_int

The rxframe_clk is used as the sampling clock for the Signal Tap.

The rx_patchk_data_error_int signal indicates a pass or fail for the ramp checker.

  • The j204c_rx_avst_valid is asserted.
  • The j204c_rx_avst_ready is asserted.
  • The rx_patchk_data_error_int signal is deasserted.
TL.2 Check the transport layer mapping of the data channel using the PRBS15 test pattern. The following signals in <ip_variant_name> _base.v are tapped:
  • j204c_rx_avst_ready
  • j204c_rx_avst_valid
  • j204c_rx_avst_data [(M*S*WIDTH_MULP*N)-1:0] 2 3 4 5
  • j204c_rx_avst_control [(M*S*WIDTH_MULP*CS)-1:0] 2 3 4 6
  • rx_patchk_data_error_int

The rxframe_clk is used as the sampling clock for the Signal Tap.

The rx_patchk_data_error_int signal indicates a pass or fail for the ramp checker.

  • The j204c_rx_avst_valid is asserted.
  • The j204c_rx_avst_ready is asserted.
  • The rx_patchk_data_error_int signal is deasserted.
2 M is the number of converters.
3 S is the number of transmitted samples per converter per frame.
4 WIDTH_MULP is the data width multiplier between the application layer and transport layer.
5 N is the number of conversion bits per converter.
6 CS is the number of control bits per conversion samples.
Level Two Title