AN 927: JESD204C Intel® FPGA IP and ADI AD9081 MxFE* ADC Interoperability Report for Intel® Stratix® 10 E-Tile Devices

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ID 683652
Date 9/28/2020
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Document Table of Contents
Document Table of Contents x
1. JESD204C Intel® FPGA IP and ADI AD9081 MxFE* ADC Interoperability Checkout Report for Intel® Stratix® 10 E-tile Devices
1. JESD204C Intel® FPGA IP and ADI AD9081 MxFE* ADC Interoperability Checkout Report for Intel® Stratix® 10 E-tile Devices x
1.1. Hardware Requirements 1.2. Hardware Setup 1.3. Hardware Checkout Methodology 1.4. JESD204C Intel® FPGA IP and ADC Configurations 1.5. Test Results 1.6. Test Result Comments 1.7. Document Revision History for AN 927: JESD204C Intel® FPGA IP and ADI AD9081 MxFE* ADC Interoperability Report for Intel® Stratix® 10 E-Tile Devices 1.8. Appendix
1.3. Hardware Checkout Methodology x
1.3.1. Receiver Data Link Layer 1.3.2. Receiver Transport Layer (TL) 1.3.3. Deterministic Latency - Subclass 1 (DL)
1.3.1. Receiver Data Link Layer x
1.3.1.1. Sync Header Alignment (SHA) 1.3.1.2. Extended Multiblock Alignment (EMBA)
1. JESD204C Intel® FPGA IP and ADI AD9081 MxFE* ADC Interoperability Checkout Report for Intel® Stratix® 10 E-tile Devices

1.4. JESD204C Intel® FPGA IP and ADC Configurations

The JESD204C Intel® FPGA IP parameters (L, M, and F) in this hardware checkout are natively supported by the AD9081 device. The transceiver data rate, sampling clock, and other JESD204C parameters comply with the AD9081 operating conditions.

The hardware checkout testing implements the JESD204C Intel® FPGA IP with the following parameter configuration.

Global setting for all configuration:
  • CF = 0
  • CS = 0
  • Subclass = 1
  • SH_CONFIG = CRC-12
  • FPGA Management Clock (MHz) = 100
Note: The other configurations are retained at default values.
Table 5.  Parameter Configuration
LMF N NP S HD E ADC Sampling Clock (MHz) FPGA Device Clock (MHz) 7 FPGA Link Clock (MHz) 8 FPGA Frame Clock (MHz)8 Lane Rate (Gbps) Decimation Factor Data Pattern
841 16 16 1 1 1 3000.00 375.00 187.50 375.00 24.75000 1 PRBS15 Ramp
8.16.4 16 16 1 0 1 2480.00 310.00 155.00 155.00 20.46000 4 PRBS15 Ramp
886 12 12 4 0 3 2949.12 184.32 92.16 368.64 12.16512 3 PRBS15 Ramp
821 16 16 2 1 1 2949.12 184.32 92.16 368.64 12.16512 1 PRBS15 Ramp
882 16 16 1 0 1 2949.12 245.76 122.88 122.88 16.22016 3 PRBS15 Ramp
442 16 16 1 0 1 3360.00 280.00 140.00 140.00 18.48000 3 PRBS15 Ramp
484 16 16 1 0 1 2949.12 184.32 92.16 92.16 12.16512 8 PRBS15 Ramp
823 12 12 8 0 3 2949.12 276.48 69.12 276.48 9.12384 1 PRBS15 Ramp
882 16 16 1 0 1 2949.12 245.76 61.44 61.44 8.11008 6 PRBS15 Ramp
821 16 16 2 1 1 3072.00 192.00 96.00 384.00 12.67200 1 PRBS15 Ramp
6.12.4 16 16 1 0 1 2760.00 345.00 172.50 172.50 22.77000 4 PRBS15 Ramp
364 16 16 1 0 1 2700.00 225.00 112.50 112.50 14.85000 6 PRBS15 Ramp
288 16 16 1 0 1 2880.00 180.00 90.00 90.00 11.88000 16 PRBS15 Ramp
7 The device clock frequency of the E-tile transceiver is the same as the core PLL of the JESD204C Intel® FPGA IP.
8 The frame clock and link clock are derived from the device clock by using an internal core PLL.
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