AN 927: JESD204C Intel® FPGA IP and ADI AD9081 MxFE* ADC Interoperability Report for Intel® Stratix® 10 E-Tile Devices

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ID 683652
Date 9/28/2020
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Document Table of Contents
Document Table of Contents x
1. JESD204C Intel® FPGA IP and ADI AD9081 MxFE* ADC Interoperability Checkout Report for Intel® Stratix® 10 E-tile Devices
1. JESD204C Intel® FPGA IP and ADI AD9081 MxFE* ADC Interoperability Checkout Report for Intel® Stratix® 10 E-tile Devices x
1.1. Hardware Requirements 1.2. Hardware Setup 1.3. Hardware Checkout Methodology 1.4. JESD204C Intel® FPGA IP and ADC Configurations 1.5. Test Results 1.6. Test Result Comments 1.7. Document Revision History for AN 927: JESD204C Intel® FPGA IP and ADI AD9081 MxFE* ADC Interoperability Report for Intel® Stratix® 10 E-Tile Devices 1.8. Appendix
1.3. Hardware Checkout Methodology x
1.3.1. Receiver Data Link Layer 1.3.2. Receiver Transport Layer (TL) 1.3.3. Deterministic Latency - Subclass 1 (DL)
1.3.1. Receiver Data Link Layer x
1.3.1.1. Sync Header Alignment (SHA) 1.3.1.2. Extended Multiblock Alignment (EMBA)
1. JESD204C Intel® FPGA IP and ADI AD9081 MxFE* ADC Interoperability Checkout Report for Intel® Stratix® 10 E-tile Devices

1.2. Hardware Setup

An Intel® Stratix® 10 TX SI Development Kit (Production Rev B Edition) is used with the ADI AD9081 daughter card module installed to the FMC+ connector of the development board.

  • The AD9081 EVM derives power from the S10 board through the FMC+ connector.
  • The E-tile transceiver reference clock of the FPGA is also supplied by the Silicon Labs Si5341 programmable clock generator present in the Intel® Stratix® 10 development kit.
  • The Si5341 programmable clock generator provides a reference clock to the HMC7044 programmable clock generator present in the AD9081 EVM through FPGA (to convert differential clock from Si5431 to single ended clock for HMC7044) and SMA to SMP cable.
  • The HMC7044 programmable clock generator provides the AD9081 device reference clock. The phase-locked loop (PLL) present in the AD9081 device generates the desired ADC sampling clock from the device reference clock.
  • The PLL reference clock of the JESD204C Intel® FPGA IP is supplied by the HMC7044 programmable clock generator through the FMC+ connector.
  • For Subclass 1, the HMC7044 clock generator generates the SYSREF signal for the AD9081 device and for the JESD204C Intel® FPGA IP through the FMC+ connector.
  • The rx_dl_signal signal is connected in between the output of the FPGA and the ADC 0 input of AD9081 through a voltage divider circuit with the SMA to SMA cables to measure the deterministic latency.
Note: Intel® recommends the SYSREF to be provided by the clock generator that sources the JESD204C Intel® FPGA IP device clock and sampling clock to ADC.
Figure 1. Hardware Setup

The following system-level diagram shows how the different modules are connected in this design.

Figure 2. System Diagram

In this setup, where LMF = 841, the data rate of transceiver lanes is 24.75 Gbps. The SYSREF and clocking scheme for FPGA and ADC is explained below and illustrated in Figure 2.

The Si5341 out8 generates 375 MHz clock to E-Tile transceiver reference clock. The 122.88 MHz differential output clock generated by the Si5341 out2 is fed to FPGA and taken out of FPGA as a single ended clock connected to CLK OUT SMA port J33 in the development kit for the HMC7044 EXT_HMCREF SMP port in AD9081 EVM through a cable. The HMC7044 takes the 122.88 MHz reference clock and generates 375 MHz for the device clock CLKIN of AD9081 and a periodic SYSREF signal of 11.71875 MHz for the SYSREF input of AD9081. The HMC7044 also generates 375 MHz for the FPGA core PLL reference clock and a periodic SYSREF signal of 11.71875 MHz for JESD204C Intel® FPGA IP through the FMC+ connector.

The JESD204C Intel® FPGA IP is instantiated in duplex mode but only the receiver path is used. For FCLK_MULP = 2, WIDTH_MULP = 8, S = 1 the core PLL generates 187.5 MHz link clock and 375 MHz frame clock.

The rx_dl_signal signal from CLK OUT SMA port J31 to ADC0/None SMA port is for the deterministic latency measurement.

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