Visible to Intel only — GUID: bnq1527495698761
Ixiasoft
Key Features
This reference design provides the following key features:
- A single-link transmission or reception of the SDI II video data at data rates up to 3 Gbps. The auto-detect and auto-switch features of the SDI II Intel® FPGA IP core allow you to switch easily between the following triple-rate SDI II standards:
- SD-SDI II at 270 Mbps
- HD-SDI II at 1.485/1.4835 Gbps
- 3G-SDI II at 2.97/2.967 Gbps
- A simplex TX channel and a simplex RX channel. Each channel has its own design components. For more information, refer to the Design Components section.
- TX channel design components:
- Transceiver Native PHY IP core in TX simplex mode
- SDI II transmitter
- TX channel transceiver PHY reset controller
- TX PLL with 297-MHz reference clock
- RX channel design components:
- Transceiver Native PHY IP core in RX simplex mode
- SDI II receiver
- RX channel transceiver PHY reset controller
- RX reconfiguration management
- TX channel design components:
- Tune the TX reference clock using the F-sync, V-sync, and H-sync input reference timing signals sourced from the SDI II Intel® FPGA IP receiver. A 27-MHz clock is generated from the FVH video sync and is feed into the ultra-low jitter PLL (LMK 03328). The LMK 03328 generates a 297/296.70-MHz output for the TX PLL reference clock at the FPGA.
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