| SDI II Intel® FPGA IP core |
- TX—receives the video data from the top level and encodes the necessary information (for example, line number (LN), cyclic redundancy check (CRC), payload ID) into the data stream.
- RX—receives the parallel data from the Transceiver Native PHY Intel® FPGA IP core and decodes the necessary information (for example, descrambling, realigning data).
|
| Transceiver Native PHY for Intel® Arria® 10/Cyclone 10 FPGA IP core |
- TX:
- Hard transceiver block that receives parallel data from the SDI II Intel® FPGA IP core and serializes the data before transmission.
- Enable the simplified data interface option—connects the parallel data directly to the tx_dataout signal of the SDI II Intel® FPGA IP core.
- RX:
- Hard transceiver block that receives serial data from an external video source.
- Enable the simplified data interface option—connects the parallel data directly to the rx_datain signal of the SDI II Intel® FPGA IP core.
|
| Transceiver PHY Reset Controller Intel® FPGA IP core |
- TX:
- The reset input of this controller is triggered from the top level.
- The controller generates the corresponding analog and digital reset signal to the Transceiver Native PHY Intel® Cyclone® 10 GX FPGA IP core, according to the reset sequencing inside the block.
- Use the tx_ready output signal from the block as a reset signal to the TX core to indicate that the transceiver is up and running, and ready to receive data from the core.
- RX:
- The reset input of this controller is triggered by the SDI II Intel® FPGA IP core.
- The controller generates the corresponding analog and digital reset signal to the Transceiver Native PHY Intel® Cyclone® 10 GX FPGA IP core, according to the reset sequencing inside the block.
|
| TX PLL |
Transmitter phase-locked loop (PLL) block that provides the serial fast clock to the Transceiver Native PHY Intel® Cyclone® 10 GX FPGA IP core. This reference design uses the Transceiver CMU PLL Intel® Cyclone® 10 GX FPGA IP core. |
| RX Reconfiguration Management |
RX transceiver reconfiguration management block that reconfigures the Transceiver Native PHY Intel® Cyclone® 10 GX FPGA IP core to receive different data rates from SD-SDI to 3G-SDI standards. |
| Loopback FIFO |
This block contains a dual-clock FIFO (DCFIFO) buffer to handle the data transmission across asynchronous clock domains—the receiver recovered clock and transmitter clock out.
- The receiver sends the decoded RX data to the transmitter through this FIFO buffer.
- When the receiver locks, the RX data is written to the FIFO buffer.
- The transmitter starts reading, encoding, and transmitting the data when half of the FIFO buffer is filled.
|