AN 886: Intel® Agilex™ Device Design Guidelines

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ID 683634
Date 8/26/2022
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Document Table of Contents
Document Table of Contents x
1. Introduction to the Intel® Agilex™ Device Design Guidelines 2. System Specification 3. Device Selection 4. Security Considerations 5. Design Entry 6. Board and Software Considerations 7. Design Implementation, Analysis, Optimization, and Verification 8. Debugging 9. Embedded Software Design Guidelines for Intel® Agilex™ SoC FPGAs
1. Introduction to the Intel® Agilex™ Device Design Guidelines x
1.1. Design Flow 1.2. Introduction to the Intel® Agilex™ Device Design Guidelines Revision History
2. System Specification x
2.1. Design Specifications 2.2. Install Intel® Quartus® Prime Software 2.3. IP Selection 2.4. Simulation 2.5. Preparing for Design Entry 2.6. I/O Summary 2.7. Using Intel® Agilex™ HPS in your Device 2.8. System Specification Revision History
2.3. IP Selection x
2.3.1. Evaluate Available HPS IP 2.3.2. Select Soft IP and I/O Interfaces
2.3.2. Select Soft IP and I/O Interfaces x
2.3.2.1. IP Cores
2.5. Preparing for Design Entry x
2.5.1. Coding Styles and Design Recommendations 2.5.2. Platform Designer
3. Device Selection x
3.1. Device Variant 3.2. PLLs and Clock Routing 3.3. Logic, Memory, and Multiplier Density 3.4. I/O Pin Count, LVDS SERDES Channels, and Package Offering 3.5. Speed Grade 3.6. Vertical Device Migration 3.7. Device Selection Revision History
4. Security Considerations x
4.1. Security Considerations Revision History
5. Design Entry x
5.1. Design Entry for SoC Devices 5.2. Design Entry for FPGA-only Devices 5.3. EMIF Considerations 5.4. Nios® II 5.5. Transceiver Planning 5.6. Reconfiguration 5.7. Design Entry Revision History
5.1. Design Entry for SoC Devices x
5.1.1. Firewall Planning 5.1.2. Boot And Configuration Considerations 5.1.3. HPS Clocking and Reset Design Considerations 5.1.4. Reset Configuration 5.1.5. HPS Pin Multiplexing Design Considerations 5.1.6. HPS I/O Settings: Constraints and Drive Strengths 5.1.7. Design Guidelines for HPS Interfaces 5.1.8. Interfacing between the FPGA and HPS 5.1.9. Implementing the Intel® Agilex™ HPS Component
5.1.2. Boot And Configuration Considerations x
5.1.2.1. Selecting HPS Boot Options 5.1.2.2. Configuration Sources 5.1.2.3. Remote System Update (RSU)
5.1.3. HPS Clocking and Reset Design Considerations x
5.1.3.1. HPS Clock Planning 5.1.3.2. Early Pin Planning and I/O Assignment Analysis 5.1.3.3. Pin Features and Connections for HPS Clocks, Reset and PoR 5.1.3.4. Direct to Factory Pin Support for Remote System Update (RSU) Feature 5.1.3.5. Internal Clocks 5.1.3.6. HPS Peripheral Reset Management
5.1.4. Reset Configuration x
5.1.4.1. HPS Peripheral Reset Management 5.1.4.2. System Reset Considerations
5.1.7. Design Guidelines for HPS Interfaces x
5.1.7.1. Design Considerations for Selecting PHY Interfaces 5.1.7.2. USB Interface Design Guidelines 5.1.7.3. SD/MMC and eMMC Card Interface Design Guidelines 5.1.7.4. Design Guidelines for Flash Interfaces 5.1.7.5. UART Interface Design Guidelines 5.1.7.6. I2C Interface Design Guidelines
5.1.7.1. Design Considerations for Selecting PHY Interfaces x
5.1.7.1.1. HPS EMAC PHY Interfaces 5.1.7.1.2. RMII and RGMII PHY Interfaces 5.1.7.1.3. PHY Interfaces Connected Through FPGA I/O 5.1.7.1.4. Consider Device Driver Availability 5.1.7.1.5. MDIO 5.1.7.1.6. Signal Integrity
5.1.7.4. Design Guidelines for Flash Interfaces x
5.1.7.4.1. NAND Flash Interface Design Guidelines
5.1.8. Interfacing between the FPGA and HPS x
5.1.8.1. Overview of HPS Memory-Mapped Interfaces 5.1.8.2. Recommended System Topologies 5.1.8.3. Recommended Starting Point for HPS-to-FPGA Interface Designs 5.1.8.4. Information on How to Configure and Use the Bridges
5.1.8.1. Overview of HPS Memory-Mapped Interfaces x
5.1.8.1.1. HPS-to-FPGA Bridge 5.1.8.1.2. Lightweight HPS-to-FPGA Bridge 5.1.8.1.3. FPGA-to-HPS Bridge 5.1.8.1.4. Interface Bandwidths
5.1.8.2. Recommended System Topologies x
5.1.8.2.1. System Level Cache Coherency 5.1.8.2.2. HPS Accesses to FPGA Fabric 5.1.8.2.3. MPU Sharing Data with FPGA 5.1.8.2.4. Examples of Cacheable and Non-Cacheable Data Accesses From the FPGA
5.2. Design Entry for FPGA-only Devices x
5.2.1. Clocking and Reset Design Considerations 5.2.2. I/O and Clock Planning
5.2.2. I/O and Clock Planning x
5.2.2.1. Making FPGA Pin Assignments 5.2.2.2. Early Pin Planning and I/O Assignment Analysis for the FPGA Device 5.2.2.3. I/O Features and Pin Connections 5.2.2.4. Clock and PLL Selection 5.2.2.5. PLL Feature Guidelines 5.2.2.6. Clock Control Features 5.2.2.7. I/O Simultaneous Switching Noise
5.2.2.3. I/O Features and Pin Connections x
5.2.2.3.1. I/O Signaling Type 5.2.2.3.2. Selectable Standards and Flexible I/O Banks 5.2.2.3.3. Dual-Purpose and Special Pin Connections 5.2.2.3.4. Intel® Agilex™ I/O Features
5.2.2.5. PLL Feature Guidelines x
5.2.2.5.1. Clock Feedback Mode 5.2.2.5.2. Clock Outputs
5.3. EMIF Considerations x
5.3.1. Memory Interfaces 5.3.2. HPS EMIF Design Considerations 5.3.3. FPGA EMIF Design Considerations
5.3.2. HPS EMIF Design Considerations x
5.3.2.1. Considerations for Connecting HPS to SDRAM 5.3.2.2. HPS EMIF I/O Locations 5.3.2.3. HPS Memory Debug
6. Board and Software Considerations x
6.1. Early System and Board Planning 6.2. Board Design Guidelines for Intel® Agilex™ SoC FPGAs 6.3. Pin Connection Considerations for Board Design 6.4. Board Considerations Revision History
6.1. Early System and Board Planning x
6.1.1. SmartVID 6.1.2. Intel® FPGA Power and Thermal Calculator 6.1.3. Thermal Management and Design 6.1.4. Temperature Sensing for Thermal Management 6.1.5. Voltage Sensor 6.1.6. Device Power-Up 6.1.7. Power Pin Connections and Power Supplies 6.1.8. Planning for Device Configuration
6.1.7. Power Pin Connections and Power Supplies x
6.1.7.1. Decoupling Capacitors 6.1.7.2. PLL Board Design Guidelines 6.1.7.3. Transceiver Board Design Guidelines
6.1.8. Planning for Device Configuration x
6.1.8.1. Device Power Cycling and Reconfiguration 6.1.8.2. Configuration Scheme Selection 6.1.8.3. Configuration Features 6.1.8.4. Intel® Quartus® Prime Configuration Settings 6.1.8.5. Configuration Pin Connections
6.1.8.2. Configuration Scheme Selection x
6.1.8.2.1. Serial Configuration Devices 6.1.8.2.2. Download Cables
6.1.8.4. Intel® Quartus® Prime Configuration Settings x
6.1.8.4.1. Optional Configuration Pins 6.1.8.4.2. Dual Purpose Configuration Pins
6.1.8.5. Configuration Pin Connections x
6.1.8.5.1. Configuration Pin Voltage Level 6.1.8.5.2. Clock Trace Signal Integrity 6.1.8.5.3. JTAG Pins 6.1.8.5.4. MSEL Configuration Mode Pins 6.1.8.5.5. Other Configuration Pins
6.2. Board Design Guidelines for Intel® Agilex™ SoC FPGAs x
6.2.1. Boundary Scan for HPS 6.2.2. Embedded Software Debugging and Trace
6.3. Pin Connection Considerations for Board Design x
6.3.1. Board-Related Intel® Quartus® Prime Settings 6.3.2. Signal Integrity Considerations 6.3.3. Board-Level Simulation and Advanced I/O Timing Analysis
6.3.1. Board-Related Intel® Quartus® Prime Settings x
6.3.1.1. Unused Pins
6.3.2. Signal Integrity Considerations x
6.3.2.1. High-Speed Board Design 6.3.2.2. Voltage Reference Pins 6.3.2.3. Simultaneous Switching Noise 6.3.2.4. I/O Termination
7. Design Implementation, Analysis, Optimization, and Verification x
7.1. Selecting a Synthesis Tool 7.2. Device Resource Utilization Reports 7.3. Intel® Quartus® Prime Messages 7.4. Timing Constraints and Analysis 7.5. Area and Timing Optimization 7.6. Preserving Performance and Reducing Compilation Time 7.7. Designing with Intel® Hyperflex™ 7.8. Simulation 7.9. Power Analysis 7.10. Power Optimization 7.11. Design Implementation, Analysis, Optimization, and Verification Revision History
7.4. Timing Constraints and Analysis x
7.4.1. Recommended Timing Optimization and Analysis Assignments
7.10. Power Optimization x
7.10.1. Device and Design Power Optimization Techniques 7.10.2. Intel® Quartus® Prime Power Optimization Techniques
7.10.1. Device and Design Power Optimization Techniques x
7.10.1.1. Device Speed Grade 7.10.1.2. Clock Power Management 7.10.1.3. Memory Power Reduction 7.10.1.4. I/O Power Guidelines
7.10.2. Intel® Quartus® Prime Power Optimization Techniques x
7.10.2.1. Power Optimization Advisor
8. Debugging x
8.1. On-Chip Debug Overview 8.2. On-Chip Debugging Tools 8.3. Debugging Revision History
8.1. On-Chip Debug Overview x
8.1.1. Planning Guidelines for Debugging Tools
9. Embedded Software Design Guidelines for Intel® Agilex™ SoC FPGAs x
9.1. Overview 9.2. Golden Hardware Reference Design (GHRD) 9.3. Define Software Requirements 9.4. Define Software Architecture 9.5. Selecting Software Tools 9.6. Choosing the Bootloader Software 9.7. Selecting an Operating System for Your Application 9.8. Assembling Your Software Development Platform for Linux* 9.9. Assembling your Software Development Platform for Partner OS or RTOS 9.10. Driver Considerations 9.11. Boot And Configuration Considerations 9.12. System Reset Considerations 9.13. Flash Considerations 9.14. Develop Application 9.15. Test and Validate 9.16. Embedded Software Design Guidelines Revision History
9.5. Selecting Software Tools x
9.5.1. Selecting Software Build Tools 9.5.2. Selecting Software Debug Tools 9.5.3. Selecting Software Trace Tools
9.7. Selecting an Operating System for Your Application x
9.7.1. Using Linux* or RTOS 9.7.2. Using the Bootloader as a Bare-Metal Framework 9.7.3. Using Symmetrical vs. Asymmetrical Multiprocessing (SMP vs. AMP) Modes
9.8. Assembling Your Software Development Platform for Linux* x
9.8.1. Golden System Reference Design (GSRD) for Linux* 9.8.2. Source Code Management Considerations
9.11. Boot And Configuration Considerations x
9.11.1. Configuration Sources 9.11.2. Configuration Flash 9.11.3. Configuration Clock 9.11.4. Selecting HPS Boot Options 9.11.5. HPS Boot Sources 9.11.6. Remote System Update (RSU)
9.13. Flash Considerations x
9.13.1. Flash Programming Method 9.13.2. Using a Single flash for Both FPGA Configuration and HPS Mass Storage
1. Introduction to the Intel® Agilex™ Device Design Guidelines
2. System Specification
3. Device Selection
4. Security Considerations
5. Design Entry
6. Board and Software Considerations
7. Design Implementation, Analysis, Optimization, and Verification
8. Debugging
9. Embedded Software Design Guidelines for Intel® Agilex™ SoC FPGAs

6.1.6. Device Power-Up

Table 54.  Device Power-Up Checklist
Number Done? Checklist Item
1   Design board for power-up: All Intel® Agilex™ GPIO pins are tri-stated until the device is configured and configuration pins drive out. The transceiver pins are at high impedance before the device periphery could get programmed. Once the periphery is programmed, the termination and Vcm are set immediately after transceiver calibration is complete.
2   Design voltage power supply ramps to be monotonic.
3   Set POR time to ensure power supplies are stable.
4   Design power sequencing and voltage regulators for best device reliability. Connect the GND between boards before connecting the power supplies.
5   Pull nSTATUS pin high to VCCIO_SDM. Ensure no external component to drive nSTATUS low during power up.

The minimum current requirement for the power-on-reset (POR) supplies must be available during device power-up.

The Intel® Agilex™ device has Power-On-Reset circuitry, which keeps the device in a reset state until the power supply outputs are within the recommended operating range. The device must reach the recommended operating range within the maximum power supply ramp time. If the ramp time is not met, the device I/O pins and programming registers remain tri-stated and device configuration fails.

In Intel® Agilex™ devices, when the pin-selectable option (MSEL) is set to non FAST QSPI mode, a typical POR time setting of 4 ms or 100 ms is available.

Intel® Agilex™ devices have power-up sequencing requirements. You should consider the power-up timing and power-down timing for each rail in order to meet the power sequencing requirements.

Intel uses GND as a reference for I/O buffer designs. Connecting the GND between boards before connecting the power supplies prevents the GND on your board from being pulled up inadvertently by a path to power through other components on your board. A pulled-up GND could otherwise cause an out-of-specification I/O voltage or current condition with the Intel device.

All I/O pins in the SDM and the HPS bank, except VSIGP_0, VSIGN_0, VSIGP_1, VSIGN_1 and RREF_SDM, are in an undetermined state during device power up and power down.

All HPS data transactions should start after the device is fully powered up.

Input signals of all I/O pins, at any point during power up and power down, should not exceed the I/O buffer power supply rail of the bank where the I/O pin resides.

When using I/O pins in the GPIO bank, the pin voltage—when the device is not turned on or during power-up or power-down conditions must not exceed 1.2 V for both 1.2 V and 1.5 V VCCIO_PIO.

After the device is fully powered up, input signals of the I/O pin should not exceed the maximum DC input voltage specification as specified in the Intel® Agilex™ Device Data Sheet.

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