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1. About This Document
2. Introduction
3. Getting Started
4. Installing the OPAE Software Package
5. Identifying the Flash Image and BMC Firmware
6. Running FPGA Diagnostics
7. Running the OPAE in a Non-Virtualized Environment
8. Running the OPAE in a Virtualized Environment
9. Intel® Acceleration Stack Quick Start Guide for Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA Archives
10. Document Revision History for Intel® Acceleration Stack Quick Start Guide for Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA
A. Updating the FIM and BMC Firmware
B. Handling Graceful Thermal Shutdown
C. FPGA Device Access Permission
D. Memlock Limit
E. Hugepage Settings
F. Troubleshooting Frequently Asked Questions (FAQ)
G. Documentation Available for the Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs 1.2.1 Release
F.1. Why do I see a 'No Suitable slots found' message when running fpgaconf on my AFU image?
F.2. How do I flash the FIM or program the AFU in a multicard system?
F.3. Which environment variables are required?
F.4. What actions do I take if I see the error message 'Error enumerating resources: no driver available'?
F.5. Troubleshooting OPAE Installation on RHEL
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G. Documentation Available for the Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs 1.2.1 Release
The following documents are on the Intel FPGA web page. To access a document, click the link.
Document | Link to Access Document |
---|---|
10 Gbps Ethernet AFU Design Example User Guide | 10 Gbps Ethernet Accelerator Functional Unit (AFU) Design Example User Guide |
40 Gbps Ethernet AFU Design Example User Guide | 40 Gbps Ethernet Accelerator Functional Unit (AFU) Design Example User Guide |
Open Programmable Acceleration Engine (OPAE) C API Programming Guide | GitHub Link |
Open Programmable Acceleration Engine (OPAE) Linux Device Driver Architecture Guide | GitHub Link |
Open Programmable Acceleration Engine (OPAE) Tools Guide | GitHub Link |
Intel® Accelerator Functional Unit (AFU) Simulation Environment (ASE) User Guide | GitHub Link |
Intel® Accelerator Functional Unit (AFU) Simulation Environment (ASE) Quick Start User Guide | Intel® Accelerator Functional Unit (AFU) Simulation Environment (ASE) Quick Start User Guide |
Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual | Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual |
Accelerator Functional Unit (AFU) Developer User Guide | |
Streaming DMA Accelerator Functional Unit (AFU) User Guide | Streaming DMA Accelerator Functional Unit AFU User Guide |
Native Loopback Accelerator Functional Unit (AFU) User Guide | Native Loopback Accelerator Functional Unit (AFU) User Guide |
Networking Interface for Open Programmable Acceleration Engine (OPAE): Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA , previously known as HSSI User Guide for Intel® FPGA Programmable Acceleration Card (Intel® FPGA PAC) Intel® Arria® 10 GX FPGA | Networking Interface for Open Programmable Acceleration Engine (OPAE): Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA |
OpenCL* on Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA Quick Start User Guide | |
Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA with Intel® Arria® 10 GX FPGA Datasheet | Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA with Intel® Arria® 10 GX FPGA Datasheet |
Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs v1.2.1 Release Notes | Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs v1.2.1 Release Notes |
Security User Guide: Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA | Security User Guide: Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA |