Nios® V Processor Reference Manual

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ID 683632
Date 10/07/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Nios® V/c Processor 3. Nios® V/m Processor 4. Nios® V/g Processor 5. Nios V Processor Reference Manual Archives 6. Document Revision History for the Nios® V Processor Reference Manual
1. Overview x
1.1. Quartus® Prime Software Support
2. Nios® V/c Processor x
2.1. Processor Performance Benchmarks 2.2. Processor Pipeline 2.3. Processor Architecture 2.4. Programming Model 2.5. Core Implementation
2.3. Processor Architecture x
2.3.1. General-Purpose Register File 2.3.2. Arithmetic Logic Unit 2.3.3. Reset and Debug Signals 2.3.4. Memory and I/O Organization 2.3.5. Error Correction Code (ECC)
2.3.4. Memory and I/O Organization x
2.3.4.1. Instruction and Data Buses 2.3.4.2. Address Map
2.3.4.1. Instruction and Data Buses x
2.3.4.1.1. Instruction Manager Port 2.3.4.1.2. Data Manager Port 2.3.4.1.3. Choosing a Suitable Interface
2.4. Programming Model x
2.4.1. Privilege Levels
2.5. Core Implementation x
2.5.1. Instruction Set Reference
3. Nios® V/m Processor x
3.1. Processor Performance Benchmarks 3.2. Processor Pipeline 3.3. Processor Architecture 3.4. Programming Model 3.5. Core Implementation
3.1. Processor Performance Benchmarks x
3.1.1. Pipelined 3.1.2. Non-pipelined
3.2. Processor Pipeline x
3.2.1. Pipelined Architecture 3.2.2. Non-pipelined Architecture
3.3. Processor Architecture x
3.3.1. General-Purpose Register File 3.3.2. Arithmetic Logic Unit 3.3.3. Reset and Debug Signals 3.3.4. Control and Status Registers 3.3.5. Trap Controller 3.3.6. Memory and I/O Organization 3.3.7. RISC-V based Debug Module 3.3.8. Error Correction Code (ECC)
3.3.5. Trap Controller x
3.3.5.1. Exception Handling 3.3.5.2. Interrupt Handling
3.3.5.2. Interrupt Handling x
3.3.5.2.1. Timer and Software Interrupt Module
3.3.6. Memory and I/O Organization x
3.3.6.1. Instruction and Data Buses 3.3.6.2. Address Map
3.3.6.1. Instruction and Data Buses x
3.3.6.1.1. Instruction Manager Port 3.3.6.1.2. Data Manager Port 3.3.6.1.3. Choosing a Suitable Interface
3.3.7. RISC-V based Debug Module x
3.3.7.1. Debug Mode 3.3.7.2. Halt from Debug Module 3.3.7.3. Trigger 3.3.7.4. Abstract Commands in Debug Mode 3.3.7.5. Hardware/Software Interface
3.4. Programming Model x
3.4.1. Privilege Levels 3.4.2. Control and Status Registers (CSR) Mapping
3.4.1. Privilege Levels x
3.4.1.1. Machine Mode (M-mode) 3.4.1.2. Debug Mode (D-mode)
3.4.2. Control and Status Registers (CSR) Mapping x
3.4.2.1. Control and Status Register Field
3.5. Core Implementation x
3.5.1. Instruction Set Reference
4. Nios® V/g Processor x
4.1. Processor Performance Benchmarks 4.2. Processor Pipeline 4.3. Processor Architecture 4.4. Programming Model 4.5. Core Implementation
4.3. Processor Architecture x
4.3.1. General-Purpose Register File 4.3.2. Arithmetic Logic Unit 4.3.3. Multipy and Divide Units 4.3.4. Floating-Point Unit 4.3.5. Custom Instruction 4.3.6. Reset and Debug Signals 4.3.7. Control and Status Registers 4.3.8. Trap Controller 4.3.9. Memory and I/O Organization 4.3.10. RISC-V based Debug Module 4.3.11. Error Correction Code (ECC) 4.3.12. Branch Prediction 4.3.13. Lockstep Module
4.3.4. Floating-Point Unit x
4.3.4.1. IEEE 754 Exception Conditions 4.3.4.2. Floating Point Operations
4.3.4.2. Floating Point Operations x
4.3.4.2.1. Floating Point Classification
4.3.8. Trap Controller x
4.3.8.1. Exception Controller 4.3.8.2. Interrupt Controller
4.3.8.2. Interrupt Controller x
4.3.8.2.1. Timer and Software Interrupt Module
4.3.9. Memory and I/O Organization x
4.3.9.1. Instruction and Data Buses 4.3.9.2. Address Map 4.3.9.3. Cache Memory 4.3.9.4. Tightly Coupled Memory
4.3.9.1. Instruction and Data Buses x
4.3.9.1.1. Instruction Manager Port 4.3.9.1.2. Data Manager Port
4.3.9.3. Cache Memory x
4.3.9.3.1. Instruction Cache 4.3.9.3.2. Data Cache 4.3.9.3.3. Configurable Cache Memory 4.3.9.3.4. Bypassing Cache (Peripheral Region) 4.3.9.3.5. Using Cache Memory Effectively
4.3.9.4. Tightly Coupled Memory x
4.3.9.4.1. Instruction and Data Tightly Coupled Memory 4.3.9.4.2. Accessing Tightly Coupled Memory 4.3.9.4.3. Using Tightly Coupled Memory Effectively
4.3.10. RISC-V based Debug Module x
4.3.10.1. Debug Mode 4.3.10.2. Halt from Debug Module 4.3.10.3. Trigger 4.3.10.4. Abstract Commands in Debug Mode 4.3.10.5. Hardware/Software Interface
4.3.11. Error Correction Code (ECC) x
4.3.11.1. ECC Interface 4.3.11.2. ECC Error Injection 4.3.11.3. Affected CSR during ECC Event
4.4. Programming Model x
4.4.1. Privilege Levels 4.4.2. Control and Status Registers (CSR) Mapping
4.4.1. Privilege Levels x
4.4.1.1. Machine Mode (M-mode) 4.4.1.2. Debug Mode (D-mode)
4.4.2. Control and Status Registers (CSR) Mapping x
4.4.2.1. Control and Status Register Field
4.5. Core Implementation x
4.5.1. Instruction Set Reference
1. Overview
2. Nios® V/c Processor
3. Nios® V/m Processor
4. Nios® V/g Processor
5. Nios V Processor Reference Manual Archives
6. Document Revision History for the Nios® V Processor Reference Manual

4.3.4.2. Floating Point Operations

The table below provides a detailed summary of the FPU operations.
Table 66.  Floating Point Operation Summary
Category Operation Cycles2 Result Subnormal Rounding3 GCC Inference
Arithmetic FDIV.S 14 a ÷ b Flush-to-0 RNE a / b
FSUB.S 1 a - b Flush-to-0 RNE a - b
FADD.S 1 a + b Flush-to-0 RNE a + b
FMUL.S 2 a x b Flush-to-0 RNE a * b
FSQRT.S 12 √a Flush-to-0 Faithful 4 sqrt(a)
FMIN.S 2 (a < b) ? a : b Supported RNE fminf()
FMAX.S 2 (a < b) ? b : a Supported RNE fmaxf()
Fused Arithmetic5 FMADD.S 3 (a x b) + c Flush-to-0 RNE (a * b) + c
FMSUB.S 3 (a x b) – c Flush-to-0 RNE (a * b) - c
FNMSUB.S 3 -(a x b) + c Flush-to-0 RNE -(a * b) + c
FNMADD.S 3 -(a x b) - c Flush-to-0 RNE -(a * b) - c
Conversion FCVT.S.W / FCVT.S.WU 3 int_to_float(a) Supported None Casting
FCVT.W.S / FCVT.WU.S 3 float_to_int(a) Supported Round towards Zero Casting
Round to Nearest, ties to Max Magnitude roundf(a)
Compare FLT.S 1 (a < b) ? 1 : 0 Flush-to-0 RNE a < b
FLE.S 1 (a ≤ b) ? 1 : 0 Flush-to-0 RNE a <= b
FEQ.S 1 (a = b) ? 1 : 0 Flush-to-0 RNE a == b
Sign Injection FSGNJN.S (FNEG.S) 1 -a Supported RNE -a
FSGNJX.S (FABS.S) 1 |a| Supported RNE fabsf(a)
Classification FCLASS.S 2 Refer to topic Floating Point Classification. Supported None fpclassify(a)
Note: Assume a, b, and c as single-precision floating point values. Nios® V Processor Fused Arithmetic has a rounding stage between the multiplier and addition.
The following list describes the header in the table above:
  • Operation —Provides the name of the floating-point operation. The names match the names of the corresponding RISC-V floating-point instructions.
  • Cycle —Specifies the number of cycles it takes to execute the instruction.
  • Result—Describes the computation performed by the operation.
  • Subnormal—Describes how the operation treats subnormal inputs and subnormal outputs. Subnormals are numbers with a magnitude less than approximately 1.17549435082e-38.
  • Rounding —Describes how the FPU rounds the result.
  • GCC Inference—Shows the C code from which GCC infers the instruction operation.

Section Content
Floating Point Classification

Related Information
2 Preliminary results.
3 Round-to-Nearest, ties to Even (RNE).
4 Faithful rounding has a maximum error of 1 Unit of Least Precision (ULP) as compared to the 0.5 ULP in RNE. Faithful rounding is employed to save area and reduce the latency of FSQRT.S.
5 GCC toolchain infers Fused Arithmetic when the optimization level is -O3 or higher.
Level Two Title