Nios® V Processor Reference Manual

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ID 683632
Date 10/02/2023
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Document Table of Contents
Document Table of Contents x
1. Overview 2. Nios® V/c Processor 3. Nios® V/m Processor 4. Nios® V/g Processor 5. Nios V Processor Reference Manual Archives 6. Document Revision History for the Nios® V Processor Reference Manual
1. Overview x
1.1. Intel® Quartus® Prime Software Support
2. Nios® V/c Processor x
2.1. Processor Performance Benchmarks 2.2. Processor Pipeline 2.3. Processor Architecture 2.4. Programming Model 2.5. Core Implementation
2.3. Processor Architecture x
2.3.1. General-Purpose Register File 2.3.2. Arithmetic Logic Unit 2.3.3. Reset and Debug Signals 2.3.4. Memory and I/O Organization 2.3.5. Error Correction Code (ECC)
2.3.4. Memory and I/O Organization x
2.3.4.1. Instruction and Data Buses 2.3.4.2. Address Map
2.3.4.1. Instruction and Data Buses x
2.3.4.1.1. Instruction Manager Port 2.3.4.1.2. Data Manager Port
2.4. Programming Model x
2.4.1. Privilege Levels
2.4.1. Privilege Levels x
2.4.1.1. Machine Mode (M-mode)
2.5. Core Implementation x
2.5.1. Instruction Set Reference
3. Nios® V/m Processor x
3.1. Processor Performance Benchmarks 3.2. Processor Pipeline 3.3. Processor Architecture 3.4. Programming Model 3.5. Core Implementation
3.1. Processor Performance Benchmarks x
3.1.1. Pipelined 3.1.2. Non-pipelined
3.2. Processor Pipeline x
3.2.1. Pipelined Architecture 3.2.2. Non-pipelined Architecture
3.3. Processor Architecture x
3.3.1. General-Purpose Register File 3.3.2. Arithmetic Logic Unit 3.3.3. Reset and Debug Signals 3.3.4. Control and Status Registers 3.3.5. Exception Controller 3.3.6. Interrupt Controller 3.3.7. Memory and I/O Organization 3.3.8. RISC-V based Debug Module 3.3.9. Error Correction Code (ECC)
3.3.6. Interrupt Controller x
3.3.6.1. Timer and Software Interrupt Module
3.3.7. Memory and I/O Organization x
3.3.7.1. Instruction and Data Buses 3.3.7.2. Address Map
3.3.7.1. Instruction and Data Buses x
3.3.7.1.1. Instruction Manager Port 3.3.7.1.2. Data Manager Port
3.3.8. RISC-V based Debug Module x
3.3.8.1. Debug Mode 3.3.8.2. Halt from Debug Module 3.3.8.3. Trigger 3.3.8.4. Abstract Commands in Debug Mode 3.3.8.5. Hardware/Software Interface
3.4. Programming Model x
3.4.1. Privilege Levels 3.4.2. Control and Status Registers (CSR) Mapping
3.4.1. Privilege Levels x
3.4.1.1. Machine Mode (M-mode) 3.4.1.2. Debug Mode (D-mode)
3.4.2. Control and Status Registers (CSR) Mapping x
3.4.2.1. Control and Status Register Field
3.5. Core Implementation x
3.5.1. Instruction Set Reference
4. Nios® V/g Processor x
4.1. Processor Performance Benchmarks 4.2. Processor Pipeline 4.3. Processor Architecture 4.4. Programming Model 4.5. Core Implementation
4.3. Processor Architecture x
4.3.1. General-Purpose Register File 4.3.2. Arithmetic Logic Unit 4.3.3. Multipy and Divide Units 4.3.4. Floating-Point Unit 4.3.5. Custom Instruction 4.3.6. Reset and Debug Signals 4.3.7. Control and Status Registers 4.3.8. Exception Controller 4.3.9. Interrupt Controller 4.3.10. Memory and I/O Organization 4.3.11. RISC-V based Debug Module 4.3.12. Error Correction Code (ECC)
4.3.4. Floating-Point Unit x
4.3.4.1. IEEE 754 Exception Conditions 4.3.4.2. Floating Point Operations
4.3.4.2. Floating Point Operations x
4.3.4.2.1. Floating Point Classification
4.3.9. Interrupt Controller x
4.3.9.1. Timer and Software Interrupt Module
4.3.10. Memory and I/O Organization x
4.3.10.1. Instruction and Data Buses 4.3.10.2. Address Map 4.3.10.3. Cache Memory 4.3.10.4. Tightly Coupled Memory
4.3.10.1. Instruction and Data Buses x
4.3.10.1.1. Instruction Manager Port 4.3.10.1.2. Data Manager Port
4.3.10.3. Cache Memory x
4.3.10.3.1. Instruction Cache 4.3.10.3.2. Data Cache 4.3.10.3.3. Configurable Cache Memory 4.3.10.3.4. Bypassing Cache (Peripheral Region) 4.3.10.3.5. Using Cache Memory Effectively
4.3.10.4. Tightly Coupled Memory x
4.3.10.4.1. Instruction and Data Tightly Coupled Memory 4.3.10.4.2. Accessing Tightly Coupled Memory 4.3.10.4.3. Using Tightly Coupled Memory Effectively
4.3.11. RISC-V based Debug Module x
4.3.11.1. Debug Mode 4.3.11.2. Halt from Debug Module 4.3.11.3. Trigger 4.3.11.4. Abstract Commands in Debug Mode 4.3.11.5. Hardware/Software Interface
4.4. Programming Model x
4.4.1. Privilege Levels 4.4.2. Control and Status Registers (CSR) Mapping
4.4.1. Privilege Levels x
4.4.1.1. Machine Mode (M-mode) 4.4.1.2. Debug Mode (D-mode)
4.4.2. Control and Status Registers (CSR) Mapping x
4.4.2.1. Control and Status Register Field
4.5. Core Implementation x
4.5.1. Instruction Set Reference
1. Overview
2. Nios® V/c Processor
3. Nios® V/m Processor
4. Nios® V/g Processor
5. Nios V Processor Reference Manual Archives
6. Document Revision History for the Nios® V Processor Reference Manual

3.1.1. Pipelined

Table 16.   Nios® V/m Processor Performance Benchmarks in Intel FPGA Devices for Intel® Quartus® Prime Pro Edition Software
FPGA Used fMAX (MHz) Logic Size (ALM) Architecture Performance
DMIPS/MHz Ratio CoreMark/MHz Ratio
Intel® Cyclone® 10 262 1409 0.567 0.400
Intel® Arria® 10 269 1404
Intel® Stratix® 10 333 1627
Intel Agilex® 7 404 1594
Table 17.  Benchmark Parameters for Intel® Quartus® Prime Pro Edition Software
Parameter Settings/Description
Intel® Quartus® Prime seed Maximum performance result are based on 10 seed sweep from Intel® Quartus® Prime Pro Edition software version 23.3.
Device speed grade Fastest speed grade from each Intel FPGA device family.
Defined peripherals
  • Nios® V/m processor core (without debug module and internal timer).
  • 128 KB on-chip memory for the instruction and data bus.
  • JTAG UART Intel® FPGA IP.
  • Interval Timer Core.
Toolchain Version
  • riscv32-unknown-elf-gcc (GCC) version 12.1.0
  • CMake Version: 3.26.3
Compiler configuration
  • Compiler flags: -03
  • Assembler options: -Wa -gdwarf2
  • Compile options: -Wall -Wformat-security -march=rv32ia -mabi=ilp32
Table 18.   Nios® V/m Processor Performance Benchmarks in Intel FPGA Devices for Intel® Quartus® Prime Standard Edition Software
FPGA Used fMAX (MHz) Logic Size Architecture Performance
DMIPS/MHz Ratio CoreMark/MHz Ratio
Intel® Cyclone® IV E 139.63 2958 (LE) 0.572 0.402
Intel® Cyclone® V 162.1 1302.9 (ALM)
Intel® Arria® V 198.65 1308.5 (ALM)
Intel® Arria® V GZ 266.52 1263.9 (ALM)
Intel® Stratix® V 329.38 1280.3 (ALM)
Intel® Cyclone® 10 LP 134.44 2946 (LE)
Intel® Arria® 10 325.41 1283.1 (ALM)
Intel® MAX® 10 105.89 2997 (LE)
Table 19.  Benchmark Parameters for Intel® Quartus® Prime Standard Edition Software
Parameter Settings/Description
Intel® Quartus® Prime seed Maximum performance result are based on 10 seed sweep from Intel® Quartus® Prime Standard Edition software version 22.3.
Device speed grade Fastest speed grade from each Intel FPGA device family.
Defined peripherals
  • Nios® V/m processor core
  • 4 KB on-chip memory for the instruction bus
  • 4 KB on-chip memory for data bus
  • Avalon® Memory-Mapped Pipeline Bridge
Toolchain Version
  • riscv32-unknown-elf-gcc (GCC) version 11.2.0
  • CMake Version: 3.23.2
Compiler configuration
  • Compiler flags: -03
  • Assembler options: -Wa -gdwarf2
  • Compile options: -Wall -Wformat-security -march=rv32ia -mabi=ilp32
Intel uses the same Intel® Quartus® Prime design example for maximum performance benchmark(fMAX) and logic size benchmarks. However, the compiler settings are different for each benchmarks:
  • fMAX benchmark: superior_performance_optimized_placement_effort
  • Logic size benchmark: area_aggressive
Note: Results may vary depending on the version of the Intel® Quartus® Prime software, the version of the Nios® V processor, compiler version, target device and the configuration of the processor. Additionally, any changes to the system logic design might change the performance and LE usage. All results are generated from design built with Platform Designer.
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