Nios® V Processor Reference Manual

Download PDF
ID 683632
Date 10/02/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. Overview 2. Nios® V/c Processor 3. Nios® V/m Processor 4. Nios® V/g Processor 5. Nios V Processor Reference Manual Archives 6. Document Revision History for the Nios® V Processor Reference Manual
1. Overview x
1.1. Intel® Quartus® Prime Software Support
2. Nios® V/c Processor x
2.1. Processor Performance Benchmarks 2.2. Processor Pipeline 2.3. Processor Architecture 2.4. Programming Model 2.5. Core Implementation
2.3. Processor Architecture x
2.3.1. General-Purpose Register File 2.3.2. Arithmetic Logic Unit 2.3.3. Reset and Debug Signals 2.3.4. Memory and I/O Organization 2.3.5. Error Correction Code (ECC)
2.3.4. Memory and I/O Organization x
2.3.4.1. Instruction and Data Buses 2.3.4.2. Address Map
2.3.4.1. Instruction and Data Buses x
2.3.4.1.1. Instruction Manager Port 2.3.4.1.2. Data Manager Port
2.4. Programming Model x
2.4.1. Privilege Levels
2.4.1. Privilege Levels x
2.4.1.1. Machine Mode (M-mode)
2.5. Core Implementation x
2.5.1. Instruction Set Reference
3. Nios® V/m Processor x
3.1. Processor Performance Benchmarks 3.2. Processor Pipeline 3.3. Processor Architecture 3.4. Programming Model 3.5. Core Implementation
3.1. Processor Performance Benchmarks x
3.1.1. Pipelined 3.1.2. Non-pipelined
3.2. Processor Pipeline x
3.2.1. Pipelined Architecture 3.2.2. Non-pipelined Architecture
3.3. Processor Architecture x
3.3.1. General-Purpose Register File 3.3.2. Arithmetic Logic Unit 3.3.3. Reset and Debug Signals 3.3.4. Control and Status Registers 3.3.5. Exception Controller 3.3.6. Interrupt Controller 3.3.7. Memory and I/O Organization 3.3.8. RISC-V based Debug Module 3.3.9. Error Correction Code (ECC)
3.3.6. Interrupt Controller x
3.3.6.1. Timer and Software Interrupt Module
3.3.7. Memory and I/O Organization x
3.3.7.1. Instruction and Data Buses 3.3.7.2. Address Map
3.3.7.1. Instruction and Data Buses x
3.3.7.1.1. Instruction Manager Port 3.3.7.1.2. Data Manager Port
3.3.8. RISC-V based Debug Module x
3.3.8.1. Debug Mode 3.3.8.2. Halt from Debug Module 3.3.8.3. Trigger 3.3.8.4. Abstract Commands in Debug Mode 3.3.8.5. Hardware/Software Interface
3.4. Programming Model x
3.4.1. Privilege Levels 3.4.2. Control and Status Registers (CSR) Mapping
3.4.1. Privilege Levels x
3.4.1.1. Machine Mode (M-mode) 3.4.1.2. Debug Mode (D-mode)
3.4.2. Control and Status Registers (CSR) Mapping x
3.4.2.1. Control and Status Register Field
3.5. Core Implementation x
3.5.1. Instruction Set Reference
4. Nios® V/g Processor x
4.1. Processor Performance Benchmarks 4.2. Processor Pipeline 4.3. Processor Architecture 4.4. Programming Model 4.5. Core Implementation
4.3. Processor Architecture x
4.3.1. General-Purpose Register File 4.3.2. Arithmetic Logic Unit 4.3.3. Multipy and Divide Units 4.3.4. Floating-Point Unit 4.3.5. Custom Instruction 4.3.6. Reset and Debug Signals 4.3.7. Control and Status Registers 4.3.8. Exception Controller 4.3.9. Interrupt Controller 4.3.10. Memory and I/O Organization 4.3.11. RISC-V based Debug Module 4.3.12. Error Correction Code (ECC)
4.3.4. Floating-Point Unit x
4.3.4.1. IEEE 754 Exception Conditions 4.3.4.2. Floating Point Operations
4.3.4.2. Floating Point Operations x
4.3.4.2.1. Floating Point Classification
4.3.9. Interrupt Controller x
4.3.9.1. Timer and Software Interrupt Module
4.3.10. Memory and I/O Organization x
4.3.10.1. Instruction and Data Buses 4.3.10.2. Address Map 4.3.10.3. Cache Memory 4.3.10.4. Tightly Coupled Memory
4.3.10.1. Instruction and Data Buses x
4.3.10.1.1. Instruction Manager Port 4.3.10.1.2. Data Manager Port
4.3.10.3. Cache Memory x
4.3.10.3.1. Instruction Cache 4.3.10.3.2. Data Cache 4.3.10.3.3. Configurable Cache Memory 4.3.10.3.4. Bypassing Cache (Peripheral Region) 4.3.10.3.5. Using Cache Memory Effectively
4.3.10.4. Tightly Coupled Memory x
4.3.10.4.1. Instruction and Data Tightly Coupled Memory 4.3.10.4.2. Accessing Tightly Coupled Memory 4.3.10.4.3. Using Tightly Coupled Memory Effectively
4.3.11. RISC-V based Debug Module x
4.3.11.1. Debug Mode 4.3.11.2. Halt from Debug Module 4.3.11.3. Trigger 4.3.11.4. Abstract Commands in Debug Mode 4.3.11.5. Hardware/Software Interface
4.4. Programming Model x
4.4.1. Privilege Levels 4.4.2. Control and Status Registers (CSR) Mapping
4.4.1. Privilege Levels x
4.4.1.1. Machine Mode (M-mode) 4.4.1.2. Debug Mode (D-mode)
4.4.2. Control and Status Registers (CSR) Mapping x
4.4.2.1. Control and Status Register Field
4.5. Core Implementation x
4.5.1. Instruction Set Reference
1. Overview
2. Nios® V/c Processor
3. Nios® V/m Processor
4. Nios® V/g Processor
5. Nios V Processor Reference Manual Archives
6. Document Revision History for the Nios® V Processor Reference Manual

4.3.12. Error Correction Code (ECC)

The Nios® V/g processor core has the option to enable error detection and ECC status for the following internal RAM blocks:

  • Register file
  • Instruction cache
  • Data cache
  • Tightly coupled memories
Each RAM block has its source ID. When an ECC event occurs, the processor transmits the source ID and ECC status to the ECC interface.
  • If the ECC event is a correctable error, the processor continues to operate without correcting the error.
  • If the ECC event is an un-correctable error, the processor halts its current progress and stall. You need to reset either the processor core alone, or entire system
Note: To reset the processor core alone, you need to apply the Reset Request Interface to safely reset the Nios® V processor (Cleared of any outstanding operations). To reset the entire system, you can use the hard reset interface instead.
The ECC interface allows external logic to monitor ECC errors in the Nios® V/g processor. The interface is a conduit and made up of two output signals.
  • cpu_ecc_status: Indicates the error status.
  • cpu_ecc_source: Indicates the error source
Table 88.   cpu_ecc_status
2-bits Encoding ECC Status Effects on Software Next Action
2’b00 No ECC event None None
2’b01 Reserved Not Applicable Not Applicable
2’b10 Correctable single bit ECC error None None
2’b11 Un-correctable ECC error Likely fatal and halts processor Reset either processor or entire system
Table 89.   cpu_ecc_source
4-bits Encoding ECC Source Available
4’b0000 No ECC event Always
4’b0001 General Purpose Register (GPR) Always
4’b0010 Instruction Cache Data RAM Always
4’b0011 Instruction Cache Tag RAM Always
4’b0100 Data Cache Data RAM Always
4’b0101 Data Cache Tag RAM Always
4’b0110 Instruction TCM1 When Instruction TCM1 is present
4’b0111 Instruction TCM2 When Instruction TCM2 is present
4’b1000 Data TCM1 When Data TCM1 is present
4’b1001 Data TCM2 When Data TCM2 is present
4’b1010 Floating Point Register (FPR) When FPU is present
4’b1111 Reserved Not Applicable
Note: Due to a limitation with embedded memory blocks, the simulation model of Nios® V processor does not support ECC on Intel® Arria® 10 devices.
Related Information
Level Two Title