F-Tile Interlaken Intel® FPGA IP User Guide

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ID 683622
Date 6/21/2022
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Document Table of Contents
Document Table of Contents x
1. About the F-Tile Interlaken Intel® FPGA IP Core 2. Getting Started 3. Parameter Settings 4. Functional Description 5. Interface Signals 6. IP Registers 7. F-Tile Interlaken Intel® FPGA IP User Guide Archives 8. Document Revision History for F-Tile Interlaken Intel® FPGA IP User Guide
1. About the F-Tile Interlaken Intel® FPGA IP Core x
1.1. Features 1.2. Device Family Support 1.3. Performance and Resource Utilization 1.4. Round-trip Latency 1.5. Release Information
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Generated File Structure 2.3. Specifying the IP Core Parameters and Options 2.4. Reference and System PLL Clock for your IP Design 2.5. Simulating the IP Core 2.6. Compiling the Full Design and Programming the FPGA
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode
2.4. Reference and System PLL Clock for your IP Design x
2.4.1. System PLL Configuration
4. Functional Description x
4.1. Data Path Flow 4.2. Interlaken Look-aside Data Path Flow 4.3. Modes of Operation 4.4. Performance 4.5. IP Reset 4.6. M20K ECC Support 4.7. Out-of-Band Flow Control
4.1. Data Path Flow x
4.1.1. Interlaken TX Path 4.1.2. Interlaken RX Path
4.1.1. Interlaken TX Path x
4.1.1.1. Transmit Path Blocks 4.1.1.2. In-Band Calendar Bits on Transmit Side
4.1.2. Interlaken RX Path x
4.1.2.1. Receive Path Blocks 4.1.2.2. In-Band Calendar Bits on Receive Side 4.1.2.3. RX Errored Packet Handling
4.1.2.3. RX Errored Packet Handling x
4.1.2.3.1. Example With Errors and In-Band Calendar Bits
4.2. Interlaken Look-aside Data Path Flow x
4.2.1. Interlaken Look-aside TX Path 4.2.2. Interlaken Look-aside RX Path
4.2.1. Interlaken Look-aside TX Path x
4.2.1.1. Transmit Path Blocks
4.2.2. Interlaken Look-aside RX Path x
4.2.2.1. Receive Path Blocks 4.2.2.2. RX Error Handling
4.3. Modes of Operation x
4.3.1. Interleaved and Packet Modes 4.3.2. Multi-Segment Mode 4.3.3. Interlaken Look-aside Mode
4.3.1. Interleaved and Packet Modes x
4.3.1.1. Transmit User Data Interface Examples 4.3.1.2. Receive User Data Interface Example
4.3.2. Multi-Segment Mode x
4.3.2.1. Multi-Segment Interface Example
4.3.3. Interlaken Look-aside Mode x
4.3.3.1. Transmit User Data Interface Example 4.3.3.2. Receive User Data Interface Example
5. Interface Signals x
5.1. Clock and Reset Interface Signals 5.2. Transmit User Interface Signals 5.3. Receive User Interface Signals 5.4. Management Interface Signals 5.5. Reconfiguration Interface Signals 5.6. Interlaken Link and Miscellaneous Signals
1. About the F-Tile Interlaken Intel® FPGA IP Core
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Interface Signals
6. IP Registers
7. F-Tile Interlaken Intel® FPGA IP User Guide Archives
8. Document Revision History for F-Tile Interlaken Intel® FPGA IP User Guide

2.4.1. System PLL Configuration

For Interlaken, the NRZ mode is supported without FEC while the PAM4 mode is supported with FEC.

Instantiate the F-Tile Reference and System PLL Clocks Intel FPGA IP for your F-Tile Interlaken Intel® FPGA IP design with the following parameters:
Table 11.  System PLL IP Parameters
Parameters Value for NRZ Mode Value for PAM4 Mode (FGT) Value for PAM4 Mode (FHT)
Mode of System PLL

(syspll_mod_<m>)

User Configuration 2 User Configuration User Configuration
Refclk source

(syspll_refclk_src_<m>)

RefClk #<n> RefClk #<n> RefClk #<n>
Output frequency

(syspll_freq_mhz_<m>)

Any frequency2

Without eFIFO: 830.078125 MHz

With eFIFO: Frequency selected from user interface parameter (System PLL clock frequency).

Frequency selected from user interface parameter (System PLL clock frequency).
Enable Refclk #<n> for FGT PMA

(refclk_fgt_output_enable_<n>)

Yes Yes -
Enable FHT Common PLL <n> for FHT PMA

(cmnpll_enable_<n>)

- - Yes
Refclk frequency #<n>

(refclk_fgt_freq_mhz_<n>)

User desired refclk frequency 3 User desired refclk frequency3 -
Refclk frequency #<n>

(refclk_fht_freq_mhz_txt_<n>)

- - User desired refclk frequency3
System PLL Output Enable <n>

(systempll_output_enable_<n>)

- Yes Yes
Figure 5. Port Connection between F-Tile Reference and System PLL Clocks Intel FPGA IP and F-Tile Interlaken Intel® FPGA IP
2 This is a mandatory requirement for each F-tile if there is no other system in use.
3 The frequency must be the same as the reference clock set in F-Tile Interlaken Intel® FPGA IP.
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