F-Tile Interlaken Intel® FPGA IP User Guide

ID 683622
Date 6/21/2022
Public

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Document Table of Contents

4.2.1.1. Transmit Path Blocks

The Interlaken Look-aside mode transmit data path has the following three main functional blocks:
  • TX MAC
  • TX PCS
  • TX PMA
Figure 12. Interlaken Look-aside IP Core Transmit Path Blocks for NRZ VariationsThe figure illustrates the eight word data transfer scenario.
Figure 13. Interlaken Look-aside IP Core Transmit Path Blocks for PAM4 VariationsThe figure illustrates the eight word data transfer scenario.

TX MAC

The Interlaken Look-aside IP core TX MAC performs the following functions:
  • Populates burst and idle control words in the incoming data stream to align with the Interlaken Look-aside protocol.
  • Performs flow adaption of the data stream, repacking the data to ensure the maximum number of words is available on each valid clock cycle.
  • Calculates and inserts CRC24 bits in all burst and idle words.

TX PCS

The FPGA soft logic implements TX PCS. The PAM4 variations contain a soft logic transcoder block to work with RS-FEC (544, 514) of the TX PMA. The Interlaken IP core TX PCS block performs the following functions for each lane:
  • Inserts the meta frame words in the incoming data stream.
  • Calculates and inserts the CRC32 bits in the meta frame diagnostic words.
  • Scrambles the data according to the scrambler seed and the protocol-specified polynomial.
  • Performs 64B/67B encoding.
  • Performs asynchronous operations and transmission lane alignment using TX Align FIFO.
  • Performs the Interlaken transcoding function to support the RS-FEC (544, 514) of the TX PMA in PAM4 mode applications.

TX PMA

The Interlaken IP core TX PMA serializes the data and sends it out on the Interlaken link. TX PMA contains three RS-FEC (544,514) blocks in 6x 53.125 Gbps PAM4 mode configuration. Each RS-FEC block serves four FEC channels in the aggregate mode.