F-Tile Interlaken Intel® FPGA IP User Guide

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ID 683622
Date 6/21/2022
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Document Table of Contents
Document Table of Contents x
1. About the F-Tile Interlaken Intel® FPGA IP Core 2. Getting Started 3. Parameter Settings 4. Functional Description 5. Interface Signals 6. IP Registers 7. F-Tile Interlaken Intel® FPGA IP User Guide Archives 8. Document Revision History for F-Tile Interlaken Intel® FPGA IP User Guide
1. About the F-Tile Interlaken Intel® FPGA IP Core x
1.1. Features 1.2. Device Family Support 1.3. Performance and Resource Utilization 1.4. Round-trip Latency 1.5. Release Information
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Generated File Structure 2.3. Specifying the IP Core Parameters and Options 2.4. Reference and System PLL Clock for your IP Design 2.5. Simulating the IP Core 2.6. Compiling the Full Design and Programming the FPGA
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode
2.4. Reference and System PLL Clock for your IP Design x
2.4.1. System PLL Configuration
4. Functional Description x
4.1. Data Path Flow 4.2. Interlaken Look-aside Data Path Flow 4.3. Modes of Operation 4.4. Performance 4.5. IP Reset 4.6. M20K ECC Support 4.7. Out-of-Band Flow Control
4.1. Data Path Flow x
4.1.1. Interlaken TX Path 4.1.2. Interlaken RX Path
4.1.1. Interlaken TX Path x
4.1.1.1. Transmit Path Blocks 4.1.1.2. In-Band Calendar Bits on Transmit Side
4.1.2. Interlaken RX Path x
4.1.2.1. Receive Path Blocks 4.1.2.2. In-Band Calendar Bits on Receive Side 4.1.2.3. RX Errored Packet Handling
4.1.2.3. RX Errored Packet Handling x
4.1.2.3.1. Example With Errors and In-Band Calendar Bits
4.2. Interlaken Look-aside Data Path Flow x
4.2.1. Interlaken Look-aside TX Path 4.2.2. Interlaken Look-aside RX Path
4.2.1. Interlaken Look-aside TX Path x
4.2.1.1. Transmit Path Blocks
4.2.2. Interlaken Look-aside RX Path x
4.2.2.1. Receive Path Blocks 4.2.2.2. RX Error Handling
4.3. Modes of Operation x
4.3.1. Interleaved and Packet Modes 4.3.2. Multi-Segment Mode 4.3.3. Interlaken Look-aside Mode
4.3.1. Interleaved and Packet Modes x
4.3.1.1. Transmit User Data Interface Examples 4.3.1.2. Receive User Data Interface Example
4.3.2. Multi-Segment Mode x
4.3.2.1. Multi-Segment Interface Example
4.3.3. Interlaken Look-aside Mode x
4.3.3.1. Transmit User Data Interface Example 4.3.3.2. Receive User Data Interface Example
5. Interface Signals x
5.1. Clock and Reset Interface Signals 5.2. Transmit User Interface Signals 5.3. Receive User Interface Signals 5.4. Management Interface Signals 5.5. Reconfiguration Interface Signals 5.6. Interlaken Link and Miscellaneous Signals
1. About the F-Tile Interlaken Intel® FPGA IP Core
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Interface Signals
6. IP Registers
7. F-Tile Interlaken Intel® FPGA IP User Guide Archives
8. Document Revision History for F-Tile Interlaken Intel® FPGA IP User Guide

4.4. Performance

You can measure the performance of F-Tile Interlaken Intel® FPGA IP core in terms of the percentage of the raw bandwidth.

You can calculate the bandwidth performance by multiplying raw bandwidth with the efficiency factor using the formula below:

Actual Bandwidth = Raw Bandwidth * Efficiency Factor

The Efficiency Factor can be calculated using the formula below:

Efficiency Factor = (Encoding Efficiency) * (Framing Efficiency) * (Alignment Efficiency) * (Meta frame Efficiency) * 100% , where:
  • Encoding Efficiency: 64B/67B encoding
  • Framing Efficiency: The impact of the 8-byte control word overhead as a percentage of the frame or cell size
  • Alignment Efficiency: The impact of invalid characters inserted to pad the end of a frame to an 8-byte word boundary
  • Meta frame Efficiency: created by the Synchronization, Scrambler, State, Diagnostic, and Skip Words (assuming a meta frame length of 2K words, and not counting optional insertion of Idle Control Words for rate matching)

User efficiency examines how well the application logic occupies the full data width of the TX user data bus. This efficiency depends on the application logic implementation and transactions. Add the user efficiency to the efficiency factor equation to include efficiency degradation due to this user interface effect. You can use average efficiency numbers. Refer to Performance section of the Interlaken Protocol Definitions for more details.

The multi-segment feature of the Interlaken IP core improves the user efficiency by utilizing the user data bus more effectively.

Refer to the following example to understand how to calculate bandwidth performance.

Sample Calculation Example

This example is for the following input conditions:
  • Number of lanes= 8
  • Clock frequency = 395 MHz
  • Meta frame size= 2048 word of 64 bit/word
  • Constant burst size = 124 bytes
Use the following steps to calculate total bandwidth efficiency and actual bandwidth:
  1. Calculate the raw bandwidth using the formula below:

    Raw bandwidth= 8 lanes * 64 bits/lane * 395 MHz = 202.2 Gbps

    This example assumes constant burst size. You can use an average burst size numbers for average bandwidth efficiency calculations.

  2. Calculate each required efficiency to determine efficiency factor:
    • Encoding efficiency = 64 bits/67 bits= 0.955

      Use 64B/67B encoding to count encoding efficiency.

    • Framing efficiency = 16 words/17 words= 0.941

      124 bytes of data contain 16 Interlaken data words. One Interlaken burst control word is added to this 16 data words. Hence, the total number of words per bursts in 17.

    • Alignment Efficiency = 124 bytes/128 bytes = 0.968

      The last Interlaken data word contains only 4 bytes of valid data instead of the full 8 bytes. In this 128 bytes (16-word) burst, only 124 byte data is valid.

    • Meta frame Efficiency = 2024 words/2048 words= 0.99

      The 2048 Interlaken words contain four meta frame control words.

  3. Total bandwidth efficiency = (Encoding Efficiency) * (Framing Efficiency) * (Alignment Efficiency) * (Meta frame Efficiency) * 100% = 0.955 * 0.941 * 0.968 * 0.99= 0.869= 86.9%
  4. Actual bandwidth = Raw Bandwidth * Total bandwidth efficiency = 202.2 * 0.869 = 175.8 Gbps
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