F-Tile Interlaken Intel® FPGA IP User Guide

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ID 683622
Date 1/14/2022
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Document Table of Contents
Document Table of Contents x
1. About the F-Tile Interlaken Intel® FPGA IP Core 2. Getting Started 3. Parameter Settings 4. Functional Description 5. Interface Signals 6. IP Registers 7. F-Tile Interlaken Intel® FPGA IP User Guide Archives 8. Document Revision History for F-Tile Interlaken Intel® FPGA IP User Guide
1. About the F-Tile Interlaken Intel® FPGA IP Core x
1.1. Features 1.2. Device Family Support 1.3. Performance and Resource Utilization 1.4. Round-trip Latency 1.5. Release Information
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Generated File Structure 2.3. Specifying the IP Core Parameters and Options 2.4. Reference and System PLL Clock for your IP Design 2.5. Simulating the IP Core 2.6. Compiling the Full Design and Programming the FPGA
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode
2.4. Reference and System PLL Clock for your IP Design x
2.4.1. System PLL Configuration
4. Functional Description x
4.1. Data Path Flow 4.2. Interlaken Look-aside Data Path Flow 4.3. Modes of Operation 4.4. Performance 4.5. IP Reset 4.6. M20K ECC Support 4.7. Out-of-Band Flow Control
4.1. Data Path Flow x
4.1.1. Interlaken TX Path 4.1.2. Interlaken RX Path
4.1.1. Interlaken TX Path x
4.1.1.1. Transmit Path Blocks 4.1.1.2. In-Band Calendar Bits on Transmit Side
4.1.2. Interlaken RX Path x
4.1.2.1. Receive Path Blocks 4.1.2.2. In-Band Calendar Bits on Receive Side 4.1.2.3. RX Errored Packet Handling
4.1.2.3. RX Errored Packet Handling x
4.1.2.3.1. Example With Errors and In-Band Calendar Bits
4.2. Interlaken Look-aside Data Path Flow x
4.2.1. Interlaken Look-aside TX Path 4.2.2. Interlaken Look-aside RX Path
4.2.1. Interlaken Look-aside TX Path x
4.2.1.1. Transmit Path Blocks
4.2.2. Interlaken Look-aside RX Path x
4.2.2.1. Receive Path Blocks 4.2.2.2. RX Error Handling
4.3. Modes of Operation x
4.3.1. Interleaved and Packet Modes 4.3.2. Multi-Segment Mode 4.3.3. Interlaken Look-aside Mode
4.3.1. Interleaved and Packet Modes x
4.3.1.1. Transmit User Data Interface Examples 4.3.1.2. Receive User Data Interface Example
4.3.2. Multi-Segment Mode x
4.3.2.1. Multi-Segment Interface Example
4.3.3. Interlaken Look-aside Mode x
4.3.3.1. Transmit User Data Interface Example 4.3.3.2. Receive User Data Interface Examples
5. Interface Signals x
5.1. Clock and Reset Interface Signals 5.2. Transmit User Interface Signals 5.3. Receive User Interface Signals 5.4. Management Interface Signals 5.5. Reconfiguration Interface Signals 5.6. Interlaken Link and Miscellaneous Signals
1. About the F-Tile Interlaken Intel® FPGA IP Core
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Interface Signals
6. IP Registers
7. F-Tile Interlaken Intel® FPGA IP User Guide Archives
8. Document Revision History for F-Tile Interlaken Intel® FPGA IP User Guide

1.3. Performance and Resource Utilization

This section covers the resources and expected performance numbers for selected variations of the Interlaken IP core using the Intel® Quartus® Prime Pro Edition software. Your results may slightly vary depending on the device you select.

For a comprehensive list of supported configurations, refer to Table 1. IP Supported Combinations of Number of Lanes and Data Rates

Table 4.  Resource Utilization for Interleaved ModeThe following numbers were obtained using the Intel® Quartus® Prime Pro Edition software version 21.4.
Device Parameters Resource Utilization
Number of Lanes Data/Lane Rate (Gbps) ALMs Logic Registers M20K Blocks
Primary Secondary
Intel® Agilex™ F-tile (NRZ) 4 6.25 18161 43061 5643 28
12 10.3125 58401 114862 13131 73
4 12.5 18159 43002 5714 28
8 37900 78115 10096 52
10 47897 96171 11493 61
12 58276 114590 13337 73
4 25.78125 18254 43582 5759 28
6 29527 65604 8221 52
8 38177 79340 9917 52
10 52929 112001 12300 100
12 63347 130393 14324 100
Intel® Agilex™ F-tile (PAM4) 2 53.125 17911 47590 6936 28
2 (with eFIFO) 18156 48008 6957 28
4 37167 87165 11963 52
4 (with eFIFO) 37676 88076 11949 52
6 60926 140328 17258 100
6 (with eFIFO) 61602 141624 17407 100
Table 5.  Resource Utilization for Packet ModeThe following numbers were obtained using the Intel® Quartus® Prime Pro Edition software version 21.4.
Device Parameters Resource Utilization
Number of Lanes Data/Lane Rate (Gbps) ALMs Logic Registers M20K Blocks
Primary Secondary
Intel® Agilex™ F-tile (NRZ) 4 6.25 18128 42954 5765 28
12 10.3125 58372 114850 13114 73
4 12.5 18141 43072 5651 28
8 37915 78370 9832 52
10 47943 96532 11185 61
12 58340 114775 13177 73
4 25.78125 18295 43525 5784 28
6 29528 65404 8419 52
8 38189 79323 9911 52
10 53431 113565 12854 100
12 63245 130603 13920 100
Intel® Agilex™ F-tile (PAM4) 2 53.125 17902 47601 6897 28
2 (with eFIFO) 18138 47813 7145 28
4 37197 86973 12102 52
4 (with eFIFO) 37603 87883 12179 52
6 60894 140159 17203 100
6 (with eFIFO) 61615 141724 17107 100
Table 6.  Resource Utilization for Interlaken Look-aside ModeThe following numbers were obtained using the Intel® Quartus® Prime Pro Edition software version 21.4.
Device Parameters Resource Utilization
Number of Lanes Data/Lane Rate (Gbps) ALMs Logic Registers M20K Blocks
Primary Secondary
Intel® Agilex™ F-tile (NRZ) 12 12.5 43897 83750 10353 0
12 25.78125 44062 84505 10431 0
Intel® Agilex™ F-tile (PAM4) 6 53.125 42286 95492 13604 0
6 (with eFIFO) 42960 96576 13809 0
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