F-Tile Interlaken Intel® FPGA IP User Guide

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ID 683622
Date 1/14/2022
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Document Table of Contents
Document Table of Contents x
1. About the F-Tile Interlaken Intel® FPGA IP Core 2. Getting Started 3. Parameter Settings 4. Functional Description 5. Interface Signals 6. IP Registers 7. F-Tile Interlaken Intel® FPGA IP User Guide Archives 8. Document Revision History for F-Tile Interlaken Intel® FPGA IP User Guide
1. About the F-Tile Interlaken Intel® FPGA IP Core x
1.1. Features 1.2. Device Family Support 1.3. Performance and Resource Utilization 1.4. Round-trip Latency 1.5. Release Information
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Generated File Structure 2.3. Specifying the IP Core Parameters and Options 2.4. Reference and System PLL Clock for your IP Design 2.5. Simulating the IP Core 2.6. Compiling the Full Design and Programming the FPGA
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode
2.4. Reference and System PLL Clock for your IP Design x
2.4.1. System PLL Configuration
4. Functional Description x
4.1. Data Path Flow 4.2. Interlaken Look-aside Data Path Flow 4.3. Modes of Operation 4.4. Performance 4.5. IP Reset 4.6. M20K ECC Support 4.7. Out-of-Band Flow Control
4.1. Data Path Flow x
4.1.1. Interlaken TX Path 4.1.2. Interlaken RX Path
4.1.1. Interlaken TX Path x
4.1.1.1. Transmit Path Blocks 4.1.1.2. In-Band Calendar Bits on Transmit Side
4.1.2. Interlaken RX Path x
4.1.2.1. Receive Path Blocks 4.1.2.2. In-Band Calendar Bits on Receive Side 4.1.2.3. RX Errored Packet Handling
4.1.2.3. RX Errored Packet Handling x
4.1.2.3.1. Example With Errors and In-Band Calendar Bits
4.2. Interlaken Look-aside Data Path Flow x
4.2.1. Interlaken Look-aside TX Path 4.2.2. Interlaken Look-aside RX Path
4.2.1. Interlaken Look-aside TX Path x
4.2.1.1. Transmit Path Blocks
4.2.2. Interlaken Look-aside RX Path x
4.2.2.1. Receive Path Blocks 4.2.2.2. RX Error Handling
4.3. Modes of Operation x
4.3.1. Interleaved and Packet Modes 4.3.2. Multi-Segment Mode 4.3.3. Interlaken Look-aside Mode
4.3.1. Interleaved and Packet Modes x
4.3.1.1. Transmit User Data Interface Examples 4.3.1.2. Receive User Data Interface Example
4.3.2. Multi-Segment Mode x
4.3.2.1. Multi-Segment Interface Example
4.3.3. Interlaken Look-aside Mode x
4.3.3.1. Transmit User Data Interface Example 4.3.3.2. Receive User Data Interface Examples
5. Interface Signals x
5.1. Clock and Reset Interface Signals 5.2. Transmit User Interface Signals 5.3. Receive User Interface Signals 5.4. Management Interface Signals 5.5. Reconfiguration Interface Signals 5.6. Interlaken Link and Miscellaneous Signals
1. About the F-Tile Interlaken Intel® FPGA IP Core
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Interface Signals
6. IP Registers
7. F-Tile Interlaken Intel® FPGA IP User Guide Archives
8. Document Revision History for F-Tile Interlaken Intel® FPGA IP User Guide

6. IP Registers

The Interlaken IP core control registers are 32 bits wide and are accessible to you using the management interface, an Avalon-MM interface which conforms to the Avalon Interface Specifications. This table lists the registers available in the IP core. All unlisted locations are reserved.
Table 33.  IP Core Register Map
Offset Name R/W Description
16'h0 PCS_BASE RO
  • [31:8]—Constant “HSi” ASCII
  • [7:0]—version number
Despite its name, this register does not encode the hard PCS base address.
16'h1 LANE_COUNT RO Number of lanes.
16'h3 ELAPSED_SEC RO [23:0]—Elapsed seconds since power up. The IP core calculates this value from the management interface clock (mm_clk) for diagnostic purposes. During continuous operation, this value rolls over every 194 days.
16'h4 TX_EMPTY RO [NUM_LANES–1:0]—Transmit FIFO status (empty)
16'h5 TX_FULL RO [NUM_LANES–1:0]—Transmit FIFO status (full)
16'h6 TX_PEMPTY RO [NUM_LANES–1:0]—Transmit FIFO status (partially empty)
16'h7 TX_PFULL RO [NUM_LANES–1:0]—Transmit FIFO status (partially full)
16'h8 RX_EMPTY RO [NUM_LANES–1:0]—Receive FIFO status (empty)
16'h9 RX_FULL RO [NUM_LANES–1:0]—Receive FIFO status (full)
16'hA RX_PEMPTY RO [NUM_LANES–1:0]—Receive FIFO status (partially empty)
16'hB RX_PFULL RO [NUM_LANES–1:0]—Receive FIFO status (partially full)
16'hC MAC_CLK_KHZ RO MAC clock frequency (kHz). This register is only available in PAM4 mode variations.
16'hD RX_KHZ RO RX recovered clock frequency (kHz)
16'hE TX_KHZ RO TX serial clock frequency (kHz)
16'h10 PLL_LOCKED RO
  • Bit[16]—MAC clock PLL lock indication.
  • Bit[0]—Transmit PLL lock indication. One lock bit for all transceivers.
16'h11 FREQ_LOCKED RO [NUM_LANES–1:0]—Clock data recovery is frequency locked on the inbound data stream
16'h13 RESET RW The normal operating state for this register is all zeros, to allow automatic reset control. These bits are intended primarily for hardware debugging use. Bits 6 and 7 are convenient for monitoring long stretches of error-free operation.
  • Bit [7] = 1: Synchronously clear the TX-side error counters and sticky flags
  • Bit [6] = 1: Synchronously clear the RX-side error counters and sticky flags
The reset for Bit 6 and 7 takes at least four mm_clk cycles to take effect and eight mm_clk cycles for a 4x lane configuration design.
16'h20 ALIGN RO
  • Bit [12]—RSFEC AM sync align (Only available in PAM4 mode device variations, not valid in NRZ mode)
  • Bit [0]—TX lanes are aligned
  • Bit [1]—RX lanes are aligned
16'h21 WORD_LOCK RO [NUM_LANES–1:0]—Word (block) boundaries have been identified in the RX stream.
16'h22 SYNC_LOCK RO [NUM_LANES–1:0]—Metaframe synchronization has been achieved.
16'h23 CRC0 RO 4-bit counters indicating CRC errors in lanes [7:0].

These saturates at F, and you clear them by setting bit 6 in the RESET register.

16'h24 CRC1 RO 4-bit counters indicating CRC errors in lanes [15:8].

These saturates at F, and you clear them by setting bit 6 in the RESET register.

16'h25 CRC2 RO 4-bit counters indicating CRC errors in lanes [23:16].

These saturates at F, and you clear them by setting bit 6 in the RESET register.

16'h26 CRC3 RO 4-bit counters indicating CRC errors in lanes [31:24].

These saturates at F, and you clear them by setting bit 6 in the RESET register.

16'h28 RX_LOA RO Bit [0]—Sticky flag indicating loss of RX side lane-to-lane alignment since this bit was last cleared through the RESET register. Typically, the IP core asserts this bit in case of a catastrophic problem such as one or more lanes going down.
16'h29 TX_LOA RO Bit [0]—Sticky flag indicating loss of TX side lane to lane alignment since this bit was last cleared through the RESET register. Typically, the IP core asserts this bit in case of a TX FIFO underflow / overflow caused by a significant deviation from the expected data flow rate through the TX PCS.
16'h38 CRC32_ERR_INJECT RW [NUM_LANES–1:0]—When a bit has the value of 1, the IP core injects CRC32 errors on the corresponding TX lane. When it has the value of 0, the IP core does not inject errors on the TX lane. You must maintain each bit at the value of 1 for the duration of a meta Frame, at least, to ensure that the IP core transmits at least one CRC32 error. For NRZ mode only.
16'h80 ILKN_FEC_XCODER_TX_ILLEGAL_STATE RO This register is only available in PAM4 mode variations. Transcoder detects illegal framing bits [66:64] of the Interlaken frame layer words. This is sticky bit.
16'h81 ILKN_FEC_XCODER_RX_UNCOR_FECCW RO This register is only available in PAM4 mode variations. FEC indicates uncorrectable FEC code word error. This register saturates at 4'b1111 for each lane.
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